Single array address translator with segment and page invalidate

Details Single array address translator with segment and page invalidate Single array address translator with segment and page invalidate

1996-05-23

1997-02-18

Lane, Jack A.

G06F 1210

Patent

active

056048793

ABSTRACT:
A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator (ERAT) has two CAM fields (ESID, EPI) that independently compare an input segment identifier and an input page identifier to a stored segment identifier and a stored page identifier, respectively. The ERAT outputs a stored real address field (DATA) associated with a stored segment-stored page pair if both comparisons are equivalent. The ERAT can invalidate stored translations on the basis of segment or page granularity by requiring either a segment or a page CAM field match, respectively, during an invalidate operation.

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