Simultaneously or sequentially decoding multiple specifiers of a

Details Simultaneously or sequentially decoding multiple specifiers of a Simultaneously or sequentially decoding multiple specifiers of a

1989-02-03

1992-11-24

Anderson, Lawrence E.

Boots, shoes, and leggings

364DIG1, 3642318, 3642624, 3642476, 3649335, 3649428, 36494834, G06F 930, G06F 938

Patent

active

051670267

ABSTRACT:
In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction. Preferably, the proper initial value is obtained prior to the incrementing or decrementing of the conflicting register by putting the instruction decoder into a special IRC mode in which only one specifier is decoded per cycle, and if a specifier being decoded is a register specifier, the content of the specified register is transmitted to the execution unit. Circuitry for detecting an intra-instruction read conflict is disclosed as well as an efficient method for handling interrupts, exceptions and flushes that may occur during the processing of an instruction having an intra-instruction read conflict.

REFERENCES:
patent: Re32493 (1987-09-01), Matsumoto et al.
patent: 4241397 (1980-12-01), Strecker
patent: 4305124 (1981-12-01), Marro et al.
patent: 4454578 (1984-06-01), Matsumoto et al.
patent: 4476525 (1984-10-01), Ishii
patent: 4521851 (1985-06-01), Trubisky et al.
patent: 4530050 (1985-07-01), Fukunaga et al.
patent: 4789925 (1988-12-01), Lahti
patent: 4890218 (1989-12-01), Bram
patent: 4891753 (1990-01-01), Budde et al.
patent: 4945511 (1990-06-01), Itomitus et al.
patent: 4991078 (1991-02-01), Wilhelm et al.
Fossum et al., "An Overview of the VAX 8600 System," Digital Equipment Technical Journal, No. 1, Aut. 1985, pp. 8-23.
Troiani et al., "The VAX 8600 I Box, A Pipelined Implementation of the VAX Architecture," Digital Technical Journal, No. 1, Aug. 1985, pp. 24-42.
VAX Architecture Handbook, Digital Equipment Corporation, 1981, pp. 51-90.
Acosta et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Trans. on Computers, vol. C-35, No. 9 (Sep. 1986), pp. 815-828.
Fossum et al., "New VAX Squeezes Mainframe Power Into Mini Package", Computer Design, vol. 24, No. 3 (Mar. 1985), Littleton, Mass., pp. 173-181.
Matsumoto et al., "A High-Performance Architecture for Variable Length Instructions", Systems & Computers in Japan, No. 3 (May 1985), Washington D.C., pp. 19-28.

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