Simultaneously deposited thin film CMOS TFTs and their method of

Details Simultaneously deposited thin film CMOS TFTs and their method of Simultaneously deposited thin film CMOS TFTs and their method of

1988-11-07

1990-08-21

James, Andrew J.

Fishing, trapping, and vermin destroying

357 237, 437 40, 437 56, H01L 2978

Patent

active

049511130

ABSTRACT:
A thin film SOI CMOS device wheren the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

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