Simultaneous self-testing system

Details Simultaneous self-testing system Simultaneous self-testing system

1982-11-08

1985-04-23

Atkinson, Charles E.

Excavating

371 15, 324 73R, G01R 3128, G06F 1100

Patent

active

045134189

ABSTRACT:
The LSSD scan paths on a number of logic circuit chips are modified and connected together in series to simultaneously serve as a random signal generator and data compression circuit to perform random stimuli signature generation.

REFERENCES:
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4317200 (1982-02-01), Wakatsuki et al.
patent: 4423509 (1983-12-01), Feissel
patent: 4435806 (1984-03-01), Segers et al.
D. K. Bhavsar et al., Self-Testing by Polynomial Division, Digest of Papers, 1981 IEEE Intl. Test Conf., pp. 208-216.
P. S. Bottorff et al., Self-Testing Scheme Using Shift Register Latches, IBM Tech. Discl. Bulletin, vol. 25, No. 10, Mar. 1983, pp. 4958-4960.

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