Simultaneous sampling dual transfer channel charge coupled devic

Details Simultaneous sampling dual transfer channel charge coupled devic Simultaneous sampling dual transfer channel charge coupled devic

1982-05-14

1985-06-04

Munson, Gene M.

Electrical pulse counters, pulse dividers, or shift registers: c

Charge transfer device

Particular input or output means

377 61, 357 24, 357 59, G11C 1928, H01L 2978, H01L 2904

Patent

active

045218960

ABSTRACT:
A dual transport channel charge coupled device for coherently processing two analog signals in a bandwidth compression mode of operation, especially for use in a high resolution coherent radar system, is disclosed. An input charge injection stage is included for each transport channel. The input stages are dependently operative to simultaneously inject charge quantities correspondingly representative of concurrent samplings of the two analog signals being processed into their corresponding associated transport channels. Each transport channel comprises N multi-phase controlled stages in an in-line arrangement with the stages of one transport channel respectively corresponding to the stages of the other, the stages being operative to transport the simultaneously injected charge quantities concurrently along their corresponding channels. Further included are two output buffer amplifier stages respectively corresponding to the transport channels, which are operative to convert the charge quantities transported simultaneously from the dual channels into a coherent time series of analog signals representative thereof. More specifically, the dual input charge injection stages are dependently operative with a common sampling gate to simultaneously input charge quantities into their correspondingly associated transport channels at sampling rates up to at least 60 megahertz. Accordingly, at a subsequent time, the stored charge quantities may be transferred from the dual channel charge coupled device at a much slower rate, say on the order of 2 megahertz, for example.

REFERENCES:
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patent: 3858232 (1974-12-01), Boyle et al.
patent: 4032867 (1977-06-01), Engeler et al.
patent: 4210825 (1980-07-01), Crochiere et al.
patent: 4216574 (1980-08-01), Feist
Nagashima et al., "CCD Analog Processor" Toshiba Review No. 130 (Nov.-Dec. 1980), pp. 30-34.
Sealer et al., "A Dual Differential Charge-Coupled Analog Delay Device" IEEE J. Solid-State Circuits, vol. SC-11 (2/76), pp. 105-108.
Esser, "Peristaltic Charge Coupled Devices . . . " in Jespers et al., Eds., Solid State Imaging, Noordhoff, Leyden, 1976, pp. 343, 354-355, 364-365, 380-387, 408-411, 418-421.

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