Simultaneous placement and wiring for VLSI chips

Details Simultaneous placement and wiring for VLSI chips Simultaneous placement and wiring for VLSI chips

1983-08-12

1986-06-03

Wise, Edward J.

Boots, shoes, and leggings

364300, G06F 1520

Patent

active

045933634

ABSTRACT:
For designing the layout of a master-slice VLSI chip steps for placing components and for determining the wiring pattern interconnecting them are alternated in an iterative process. The chip area is partitioned into subareas of decreasing size, the set of components is partitioned into subsets which fit to the respective subareas, and after each partitioning step the global wiring is determined for the existing subnets of the whole network. Due to this interrelation of placement and wiring procedures, advantages with respect to total wire length, overflow number of wires, and processing time can be gained.

REFERENCES:
patent: T938005 (1975-09-01), Colton et al.
patent: T940013 (1975-11-01), Ho
patent: T940020 (1975-11-01), Brechling et al.
patent: T944001 (1976-03-01), Hanan et al.
patent: 3617714 (1971-11-01), Kernighan et al.
patent: 3681782 (1972-08-01), Scanlon
patent: 3705409 (1972-12-01), Brayton et al.
patent: 4027246 (1977-05-01), Caccoma et al.
patent: 4377849 (1983-03-01), Finger et al.
patent: 4484292 (1984-11-01), Hong et al.
patent: 4500963 (1985-02-01), Smit et al.

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