Simultaneous operation flash memory device with a flexible bank

Details Simultaneous operation flash memory device with a flexible bank Simultaneous operation flash memory device with a flexible bank

1998-09-23

1999-11-30

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular connection

36518513, 36523003, G11C 700

Patent

active

059954159

ABSTRACT:
A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

REFERENCES:
patent: 5822238 (1998-10-01), Okubo
patent: 5847998 (1998-12-01), Van Buskirk
patent: 5848012 (1998-12-01), Tsukude et al.
patent: 5867430 (1999-02-01), Chen et al.

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