Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2000-08-18
2002-08-13
Phasge, Arun S. (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S163000, C205S165000, C205S167000
Reexamination Certificate
active
06432291
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electroplating both sides of a workpiece in the form of substantially flat, electrically insulative substrate having electrically interconnected circuit patterns formed on a pair of opposed major surfaces. More particularly, the present invention relates to a method for simultaneously electroplating at least one metal or metal alloy layer on electrically interconnected patterns on both surfaces of a circuit board substrate utilized for mounting and providing electrical connections to a semiconductor integrated circuit (IC) die or chip, as in ball grid array (BGA) device packages.
BACKGROUND OF THE INVENTION
Electrical circuit boards and similar type components comprising complex, electrically interconnected circuit patterns formed on opposite sides of a planar, insulative substrate enjoy widespread utility in the manufacture of electrical and electronic components and devices. For example, an increasingly important aspect of semiconductor integrated circuit (IC) manufacturing technology is mounting of the semiconductor IC die or chip to an appropriately configured dual-sided substrate as part of a process for forming encapsulated device packages. Frequently, this requires providing the IC chip or die with as many input/output (“I/O”) terminals as is feasible. As a consequence of the requirement for a large number of terminals to be formed on a limited amount of substrate surface, so-called “ball grid array” (“BGA”) structures and bonding techniques have been developed in order to provide high areal density interconnections between the IC package and, e.g., a larger substrate.
A typical, encapsulated BGA type semiconductor IC device package (
1
) is shown in schematic, cross-sectional view in FIG.
1
. According to such BGA type packaging, an IC die or chip (
2
) is mounted on a patterned, upper solder mask layer (
3
U) formed on the upper major surface (
4
U) of a dual-sided substrate (
4
), i.e., a dual-sided printed circuit board (“PCB”) or a ceramic or composite material circuit board (“CCB”) having an upper circuit pattern (
5
U) formed thereon. A plurality of electrical connections (
6
) comprising fine electrical wires, typically of gold (Au), are connected, as by wire bonding, between the upper surface (
2
U) of the IC die or chip (
2
) and a plurality of electrical bonding pad areas (
7
B) (also termed “bond fingers”) of the upper circuit pattern (
5
U) exposed through a plurality of openings (
3
′) selectively formed in solder mask layer (
3
U). Each of the electrically conductive traces or lines forming upper circuit pattern (
5
U) is electrically connected by means of an electrically conductive plug or via (
7
V) filling a through-hole (
8
) extending through the thickness of substrate (
4
), to at least one electrically conductive trace or line of a lower circuit pattern (
5
L) formed on the lower major surface (
4
L) of the substrate. A plurality of generally circularly-shaped “ball land” areas are exposed through openings (
3
″) selectively formed in lower solder mask layer (
3
L) overlying substrate lower major surface (
4
L) for accommodating therein a spaced-apart plurality of substantially spherically-shaped electrical conductors (
9
) formed of a solder material and constituting a two-dimensional ball grid array (BGA). Finally, BGA package (
1
) includes a layer of molding material (
10
) encapsulating at least the IC die or chip (
2
).
According to BGA methodology, the device package with its substantially spherically-shaped BGA solder balls or bumps is then mated with a corresponding ball grid array (BGA) or bonding pad array formed on a substrate surface. Once mated, the solder balls or bumps of the IC device package and the corresponding solder balls or bumps or bonding pads of the substrate are heated to effect reflow and mutual bonding, whereby each solder ball or bump forms a bond between the IC device package and the substrate. As a consequence, each bonded combination functions as both an electrical and physical contact.
A variant of the above BGA bonding technology, known as “controlled collapse chip connection”, or “C
4
”, is particularly useful in applications having a very high density of electrical interconnections. According to C
4
methodology, electrically conductive balls or bumps comprising a solder material are formed on the IC device package, as well as on the mating surface of the substrate. Bonding between the two sets of solder balls or bumps is effected by application of heat and mechanical pressure to the IC device package and the substrate. The application of heat causes both sets of solder-based balls or bumps to reflow, thereby providing physical and ohmic electrical connection therebetween, while the applied mechanical pressure causes the mated pairs of solder-based balls or bumps to at least partially collapse, creating a “pancake” shape which advantageously reduces interconnection length and resistance.
An essential feature of the above-described BGA fabrication methodology is the formation of suitable dual-sided substrates (
4
) having the requisite electrically interconnected circuit patterns (
5
U,
5
L) formed on the opposing major surfaces (
4
U,
4
L), wherein the circuit patterns are provided with one or more plated layers for minimizing corrosion due to environmental factors, etc., and for facilitating wetting and adhesion of solder-type contact materials thereto. However, the continuing increase in complexity of the IC chip or die (
2
) has necessitated a parallel increase in the number of I/O connections required to be made to the IC chip or die. The increase in IC complexity has necessitated a parallel increase in the number and complexity of the requisite electrically conductive traces constituting the upper and lower circuit patterns formed on the substrate, which increase in number and complexity has in turn resulted in a substantial decrease in the inter-trace spacings.
According to conventional methodologies for manufacturing dual-sided circuit boards suitable for use in BGA type packaging applications, multi-trace electrically conductive patterns, typically of copper (Cu) or a Cu-based alloy, are formed, as by conventional techniques, on both major surfaces of a substrate comprised of at least one electrically insulative material selected from polymers, ceramics, glasses, resins, laminates, and composites thereof, e.g., an epoxy resin-fiberglass composite, and electrically interconnected by means of a plurality electrically conductive via plugs filling through-holes extending between the opposing major surfaces.
FIG. 2A
illustrates, in plan view, a corner portion of the upper major surface (
4
U) of a first example of a dual-sided substrate (
4
), wherein each of the individual traces (
5
T
U
) of upper circuit pattern (
5
U) is shown as extending from the interior portion of upper major surface (
4
U), where bond fingers (
7
B) are located, to the periphery thereof, where conductive via plugs (
7
V) are formed for electrical interconnection with the lower circuit pattern (
4
L), which pattern is not necessarily similarly configured. The thus-formed, electrically interconnected upper and lower circuit patterns (
5
U,
5
L) are then subjected to a plating process, conventionally electroplating, for depositing thereon a layer or layer system which provides corrosion resistance and facilitates low ohmic resistance bonding of solder-based electrical conductors thereto. Typically, thin layers of Ni and Au are sequentially electroplated over the Cu or Cu-based circuit patterns (
5
U,
5
L) for this purpose. According to conventional electroplating processes, at least one electrically conductive tie bar (
11
) having several lateral extensions (
11
L,
11
R), etc., is formed on at least one of the upper or lower major surfaces (
4
U or
4
L) and in electrical contact with each of the conductive traces on that surface, thereby providing a common electrical conductor for connection to a source of electroplating potential, whereby each of the electric
Fontecha Edwin R.
Newman Robert
Vivares Valerie
Advanced Micro Devices , Inc.
Phasge Arun S,.
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