Simultaneous dual access semiconductor memory device

Details Simultaneous dual access semiconductor memory device Simultaneous dual access semiconductor memory device

1987-06-19

1989-04-04

Hecker, Stuart N.

Static information storage and retrieval

Addressing

365 51, 365189, 365222, G11C 800, G11C 700, G11C 502

Patent

active

048192090

ABSTRACT:
A semiconductor memory device includes: a memory cell array constituted of a plurality of memory cell array units; transfer gates inserted in bit lines between the adjacent memory cell array units; a first and a second column decoders connected to both ends of bit lines in which the transfer gates are inserted; a row decoder connected to word lines of the memory cell array. The row decoder is adapted to be divided selectively in two parts; and two sets of row/column addresses are supplied to the column decoders and the row decoder. Therefore, simultaneous separate accesses to the memory cell array are carried out by the two sets of row/column addresses.

REFERENCES:
patent: 4742493 (1988-05-01), LeWallen et al.
patent: 4758988 (1988-07-01), Kuo
patent: 4758993 (1988-07-01), Takemae

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