Excavating
Patent
1992-03-06
1995-04-04
Beausoliel, Jr., Robert W.
Excavating
395575, 371 61, G06F 1100
Patent
active
054043603
ABSTRACT:
A simulator for simulating operations of a logical circuit has as its object the provision of a simulator capable of detailed timing error checking without impairing the simulation executing speed. A timing check primitive adding circuit, based on circuit information indicating electronic devices and loop circuits selected for timing error checking, outputs circuit information with simulation control data for controlling the simulation of only the selected devices or selected loop circuits. A timing error detection circuit and a timing error cause analyzing circuit grasp changes in test pattern input and output signals of a selected device and perform detailed timing error checking.
REFERENCES:
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5095454 (1992-03-01), Huang
patent: 5105374 (1992-04-01), Yoshida
T. Okabe, et al., "A Mixed Level Simulator With Enhanced Timing Verification Capability", Oct. 8, 1990, pp. 53-60, (with English abstract).
Suzuki Tsuneki
Yoshida Norio
Beausoliel, Jr. Robert W.
Hua Ly V.
Mitsubishi Denki & Kabushiki Kaisha
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