Simulator for conducting timing analysis of a circuit

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364488, G06F 1560

Patent

active

054002702

ABSTRACT:
There is disclosed a simulator having timing error detecting from input and output signal level changes. Different timing error verifications are carried out for respective elements. In similar constructions, different test rule error verifications are also carried out for the respective elements as a function of the contents of a test rule check value definition file.

REFERENCES:
patent: T928004 (1974-11-01), Carpenter et al.
patent: T940013 (1975-11-01), Ho
patent: 4821220 (1989-04-01), Duisberg
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5105374 (1992-04-01), Yoshida
patent: 5189365 (1993-02-01), Ikoda et al.
Mitsubishi Electric Corporation, Oct. 8, 1990, pp. 53-60, Tetsuya Okabe, et al., "A Mixed Level Simulator with Enhanced Timing Verification Capability."

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