Simulation using compiled function description language

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364490, 364578, 364DIG1, 3642323, 3642328, G06F 9455

Patent

active

054370370

ABSTRACT:
A simulation program conversion method and system is provided. The original simulation program is written by a function description language, such as Verilog-HDL, using a text editor, and, then, the original simulation program is converted into an executable program using a programming language, such as the C language, so that the simulation program may be compiled before execution. The speed of execution of the simulation program is significantly improved.

REFERENCES:
patent: 4972334 (1990-11-01), Yamabe et al.
patent: 5068812 (1991-11-01), Schaefer et al.
patent: 5084824 (1992-01-01), Lam et al.

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