Simulation of hardware based on smart buffer objects

Details Simulation of hardware based on smart buffer objects Simulation of hardware based on smart buffer objects

2007-07-10

2007-07-10

Rodriguez, Paul (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Software program

C703S014000, C703S021000, C714S038110, C717S131000, C717S135000

Reexamination Certificate

active

10422689

ABSTRACT:
Methods, articles of manufacture, and systems for software simulation of hardware, for use in testing firmware, are provided. The software simulation may be accomplished through the creation and use of a set of intelligent buffer objects (hereinafter “smart buffers”) corresponding to registers (e.g., status, control, and results registers) in actual hardware targeted by the firmware. When accessed, the smart buffers may call specialized functions (or behavior actions) designed to simulate (expected or unexpected) behavior of the targeted hardware by modifying smart buffers associated with the same or other hardware registers. The simulated behavior of the hardware may allow the firmware code to be properly exercised as if running on an actual product platform.

REFERENCES:
patent: 6842883 (2005-01-01), Whitehill
David Becker, et. al., Jun. 1992 pp. 129-134, 29thACM/IEEE 8-12, An engineering environment for hardware/software co-simulation.
Ashenden, 2002, Academic press, A harcourt science and technology company, “The designer's guide to VHDL Second Edition”.
Wanzenried, R., Mar. 1994, Verilog HDL Conference, 1994., International, pp. 29-36, Structured board level simulation using Verilog.
Ferrandi, F. et. al., Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings Mar. 13-16, 2001 pp. 403-410, Functional test generation for behaviorally sequential models.

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