Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Software program
Reexamination Certificate
2007-03-06
2007-03-06
Jones, Hugh (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Software program
C716S030000
Reexamination Certificate
active
10196702
ABSTRACT:
A method for design verification includes receiving a software model of a design of a system under evaluation, and providing a property, which is dependent on a specified variable having a predefined range of values. The property applies to all states of the system for any selected value among the values of the variable within the predefined range. The property is processed so as to generate a checker program for detecting a violation of the property. A simulation of the system is then run using the software model together with the checker program.
REFERENCES:
patent: 6493852 (2002-12-01), Narain et al.
“Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming” Vemuri, R.; Kalyanaraman, R.;Very Large Scale Integration (VLSI) Systems, IEEE Transactions on vol. 3, Issue 2, Jun. 1995 Page(s):.
“Design verification and functional testing of finite state machines” Weiss, M.W.; Seth, S.C.; Mehta, S.K.; Einspahr, K.L.; VLSI Design, 2001, Fourteenth International Conference on Jan. 3-7, 2001 pp. 189-195.
A.J. Hu, M.Y. Vardi, ‘Computer Aided Verification’,Proceedings of the 10th International conference, CAV 1998), 6 pages.
T. Schlipf, T. Buechner, R. Fritz, M. Helms, J. Koehl, ‘Formal verification made easy’,IBM Journal of Research and Development. vol. 41, No. 4/5, pp. 567-576, Jul./Sep. 1997.
I. Beer, S. Ben-David, C. Eisner, A. Landver, ‘RuleBase: an Industry-Oriented Formal Verification Tool’,Proceedings of the Design Automation Conference DAC96, Las Vegas, Nevada, 1996, 6 pages.
E.M. Clarke, Jr., O. Grumberg, D.A. Peled, ‘Model Checking’,The MIT Press, 1999, 4 pages.
K.L. McMillan (Carnegie Mellon University); ‘Symbolic Model Checking,’Kluwer Academic Publishers, 1993, 3 pages.
Beer Ilan
Keidar Sharon
Alhija Saif
Jones Hugh
Kaufman Stephen C.
LandOfFree
Simulation monitors based on temporal formulas does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simulation monitors based on temporal formulas, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simulation monitors based on temporal formulas will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3793160