Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
1999-03-10
2003-01-28
Jones, Hugh M. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S002000, C324S451000, C324S543000, C374S044000, C374S057000, C438S468000
Reexamination Certificate
active
06513000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of simulating wiring temperature rise due to a void causing the fault of refined wirings in a large scale integrated circuit. The present invention particularly relates to/a method of simulating wiring temperature rise by conducting two-dimensional thermal analysis on a wiring cross-section.
2. Description of the Related Art
The wiring fault in a large scale integrated circuit (to be referred to as “LSI” hereinafter) is caused by a phenomenon called electro-migration (to be referred to as “EM” hereinafter). The EM phenomenon occurs when aluminum atoms which constitute an LSI wiring are expelled by electrons, aluminum atoms are locally missed to cause a void in wiring, the void generally grows to fluctuate the wiring, thereby resulting in a fault. In the practical LSI wiring, current continuously flows thanks to a barrier metal intended to protect the aluminum wiring. The barrier metal is higher in specific resistance than aluminum. Due to this, if it is recognized that an increase in wiring resistance exceeds a certain level, it is judged as a wiring fault.
The characteristics of the EM phenomenon is expressed by an empirical expression (to be referred to as “MTTF” hereinafter) as shown in equation (1) below for the average life of a wiring:
MTTF
J
−n
exp (Ea/k&thgr;) (1)
In the equation (1), J is current density, &thgr; is temperature, Ea is activation energy, k is a Boltzmann's constant and n is a constant. As is seen from equation (1), the higher the current density J is or the higher the temperature &thgr; is, the more EM phenomenon is accelerated. Taking this into consideration, in the actual LSI wiring, to determine the reliability of the wiring, an acceleration test for a wiring fault is conducted at high current density and high temperature for a certain period of time. Based on the test, it is determined how long the wiring is used at the current density and temperature in a state in which an ordinary LSI is being used, to thereby determine the reliability of the wiring.
The problem with the wiring reliability test is how to determine a test temperature. In other words, since resistivity is concentrated into a portion of a void, temperature rises in the neighborhood of the void due to the local generation of Joule heat. A multi-layer wiring has, in particular, a disadvantage in that the respective wiring layers differ in temperature rise from one another. Due to this, it is necessary to correct temperatures used as parameters for the reliability test.
It is, thus, difficult to measure temperature rise if a void occurs. Temperature rise in a void portion has been conventionally measured by means of three-dimensional thermal analysis simulation. Specifically, while a thermal quantity and a constraint state are given, temperature rise is measured using three-dimensional thermal analysis simulation by a finite element method (Extended Abstracts; The Japan Society of Applied Physics and Related Societies (The 40
th
Spring Meeting, 1993) 733 by Hamashima et al.).
FIG. 1
is a flow chart showing a conventional simulation method in a case where an oxide film is formed on a silicon substrate, an aluminum wiring is formed on the oxide film and a void appears in th e wiring.
FIG. 2
is a typical view of a wiring configuration.
First, the three-dimensional wiring configuration is created as shown in
FIG. 2
(in step S
1
).
Next, it is assumed that a void occurs in the wiring in the model and the heat quantity of the void is Q
0
. While the value Q
0
is applied to the three-dimensional void in the model which has been previously created and necessary temperature constraint is given to the void, a three-dimensional thermal analysis simulation is conducted (in step S
2
).
A temperature rise distribution &thgr;
0
(x) is obtained in wiring length direction. As shown in
FIG. 3
, a graph of temperature rise versus wiring length direction is created (in step S
3
).
Thereafter, a rise &thgr;
0
(0) in the temperature of the void is read from the graph of
FIG. 3
(in step S
4
).
This conventional temperature simulation method has, however, the following disadvantages. First, the three-dimensional thermal analysis simulation takes a lot of time for analysis and calculation.
Second, the calculation amount is enormous for three-dimensional thermal analysis simulation, with the result that the capacity of a memory and that of a hard disk become high.
Further, the three-dimensional thermal analysis simulation is complicated in the input of an analysis model configuration and it takes a lot of time to create a mesh.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a wiring temperature rise simulation method capable of shortening analysis time, saving the capacity of a memory and that of a disk for use in calculation, with a simple analysis model to thereby facilitate creating a mesh.
A wiring temperature rise simulation method according to the first aspect of the present invention comprises the steps of obtaining a heat capacity C
1
by conducting a two-dimensional thermal analysis simulation to a cross-section of a wiring; and obtaining a temperature rise &thgr;
0
at a portion of the wiring in which a void occurs, based on one-dimensional approximate equation &thgr;
0
=(Q
0
/2) (&lgr;* SC
1
)
−½
along a wiring length direction, where &thgr;
0
(measured in ° K.) is a wiring temperature rise at the portion of the void, Q
0
(measured in W, i.e. Watts) is a heat quantity of the void in the wiring, &lgr; (measured in [W/(° K. m)]) is a heat conductivity of the wiring and S (measured in m
2
, i.e. meters squared) is a cross-sectional area of the wiring.
A wiring temperature rise simulation method according to the second aspect of the present application comprises the steps of obtaining a heat capacity C
1
from an equation of C
1
=&lgr;′{(W/t)+(2.80/1.15) (h/t)
0.222
}, where W is a wiring width, h is a wiring thickness, t is a substrate film thickness and &lgr;′ is a heat conductivity of the substrate file; and obtaining a wiring temperature rise &thgr;
0
based on one-dimensional approximate expression of &thgr;
0
=(Q
0
/2) (&lgr;* SC
1
)
−½
along a wiring length direction, where &thgr;
0
is a temperature rise at a portion of the wiring in which a void occurs, Q
0
is a heat quantity of the void in the wiring, &lgr; is a heat conductivity of the wiring and S is a cross-sectional area of the wiring.
According to the present invention, not the conventional three-dimensional thermal analysis simulation method but the two-dimensional thermal analysis simulation method is used. In the present method, after a heating capacity is obtained, temperature rise &thgr;
0
is obtained by the one-dimensional approximate expression in wiring length direction. It is, therefore, possible to make a model configuration simple and to thereby greatly shorten time for creating a mesh and time for analysis. It is also possible to reduce the capacity of a memory and that of a disk for use in analysis and calculation.
As stated above, according to the present invention, it is possible to estimate the temperature rise of a wiring in the vicinity of a void with the same accuracy as in the conventional three-dimensional simulation by using two-dimensional thermal analysis simulation and the one-dimensional approximate expression. Due to this, it is possible to simplify an analysis model, to greatly shorten calculation time required for analysis and to considerably save the capacity of a memory and that of a disk required for the analysis.
REFERENCES:
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patent: 4483629 (1984-11-01), Schwarz et al.
patent: 4722609 (1988-02-01), Epstein et al.
patent: 4751099 (1988-06-01), Niino et al.
patent: 5264377 (1993-11-01), Chesire et al.
patent: 5291142 (1994-03-01), Ohmi
patent: 5408638 (1995-04-01), Sagawa e
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