Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-09-10
2002-04-09
Frejd, Russell W. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S022000, C716S030000
Reexamination Certificate
active
06370493
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computers and more particularly to systems and methods of generating data for testing an integrated circuit chip.
2. Description of Related Art
Microelectronic integrated circuits (ICs), such as computer chips, are used in a variety of products including personal computers, automobiles, communication systems, and consumer electronics products. To produce an IC, a manufacturer must first design an electronic circuit to integrate (i.e., manufacture) into a chip. This stage of the design process typically requires a designer to simulate a circuit description in a circuit simulator and compare the simulated results with expected results to verify the proper operation of the circuit design. A circuit design representation, such as a circuit netlist or a Register Transfer Level (RTL) description, is input into the simulator to describe the circuit to be simulated. A netlist is typically a list of electronic logic cells with a description of the connections between the inputs and the outputs of the various logic cells. An RTL description is a description of the functionality of the circuit, much like programming source code is a description of the functionality of a software program.
To simulate the circuit, the designer must also provide input stimulus to the simulation. Input stimulus represents a set of input signals required to drive specific functional aspects of the circuit during simulation. Generally, the input stimulus used in circuit simulation is created by the designer to simulate and verify the operation of the circuit design embodied in the design representation. The input stimulus is primarily based on anticipated real world conditions (e.g., the conditions of an IC found in a cellular phone) and on requirements for properly exercising particular functional blocks within the circuit.
After a circuit is designed, it is manufactured into an IC by way of a microelectronics fabrication process. Fabrication involves multiple stages of chemical processing to create a physical IC having, for example, solid state transistors, solid state resistors, input/output pads, metal interconnections and so on. Various design, manufacturing, and operational conditions can cause a manufactured IC to perform incorrectly after it has been fabricated. Therefore, an IC manufacturer typically tests the operation of every IC it produces to verify proper operation. The testing of an IC typically requires high speed testers, typically called Automated Test Equipment (ATE) systems, that can test hundreds of chips per hour. Like circuit simulators, ATE systems also require input and output information (called “test patterns”) to drive the IC and to verify results during testing.
During simulation of IC designs, significant computer runtime is generally required to ascertain strengths and logic states of signals at input, output, and bi-directional pins of an IC. Typically, the simulator or an associated program determines the signal information by querying the simulator and then outputs the resulting logic states to an output file, an output data structure, or database. Conventional algorithms analyze the states of all pins at each iteration. Generally, the more input, output, and bi-directional pins in the IC design, the longer the runtime. The problem with conventional algorithms employed to perform this task lies in excessive looping through each signal in an IC design, which increases the runtime of the simulation. Because the modern trend in ICs involves rapidly increasing pin counts, the impact of the conventional algorithm's inefficiency is becoming too costly to ignore. Therefore, there is a need for a simpler and more time efficient method for ascertaining the strengths and logic states of input and output signals in an IC in order to reduce the overall runtime of simulation programs.
SUMMARY OF THE INVENTION
The primary object of the invention is to provide a formatting program for a simulation program that includes a method of pin testing that reduces the runtime, memory usage and output file size of tests performed on IC designs under simulation.
The present invention is preferably embodied by a software program that asks a simulator which pin strengths in a design, if any, have changed rather than analyzing the signal strengths and logic states for each pin in the design at each iteration, i.e., at each simulation time stamp. If no pin strength changes since the previous time stamp, the event is ignored and the time stamp is increased until a pin strength change is detected. After such a pin strength change is detected, the input, output, or bi-directional signal can then be processed and output for use by another design or test tool This technique drastically reduces the runtime, memory usage, and output file size of a simulation.
A program in accordance with the present invention is linkable with conventional simulator programs. It provides a quick and accurate method of reporting the logic states of input, output, and bi-directional pins for verification of design accuracy. The program can be called in the testbench of the simulation. A test bench is a set of instructions that configure and initiate a simulation.
A program in accordance with the present invention produces a print on change file that stores logic values associated with pins of a circuit design in accordance with specified time stamps. A program in accordance with the present invention asks the simulator which pin strengths in a design, if any, have changed. If a pin strength change has occurred, then the program retrieves a corresponding number that identifies a pin with a changed pin strength. Using the retrieved number, the program then asks the simulator for strength contributions of the pin's signal and maps the strengths to an appropriate logic state. The resulting logic state and the corresponding pin are printed in an output file according to the time stamp in which the change was detected.
The method in accordance with the present invention ignores a pin until it changes, which reduces the computer runtime by avoiding unnecessary testing of the strength of every pin in the design at each time stamp. The program method of the invention is only concerned with changes of state and strength. The method queries the simulator to return just the pins that have changed strengths. The method then retrieves the strength contributions (“strength1” and “strength0”) for the returned pins and maps these strength contributions to a logic state that is output to an output file.
Other objects, features and advantages of the present invention will become apparent from a reading of the following detailed description when taken in conjunction with the accompanying drawing wherein a particular embodiment of the invention is disclosed as an illustrative example.
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Knapp Kevin L.
Laake Kevin M.
Frejd Russell W.
LSI Logic Corporation
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