Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Patent
1998-06-02
2000-11-07
Stamber, Eric W.
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
703 15, 703 16, 708446, G06F 1750
Patent
active
061449326
ABSTRACT:
A simulation device comprises an equation generating unit for generating a simultaneous linear equation by application of the implicit integration formula and the Newton iteration method to the description data of an electronic circuit to be simulated, a plurality of block ILU factorization units for performing incomplete LU factorization processing in parallel on each block in a coefficient matrix of the generated simultaneous linear equation, a plurality of fill-in adding units for adding a plurality of fills-in generated by the incomplete LU factorization to a combined portion of coefficient matrices, in parallel, a plurality of line collection ILU factorization units for ILU-factorizing each of several line collections on the combined portion where the fills-in are added, and a convergent solution judging unit for repeating a series of the above processing until convergence of a solution in the simultaneous linear equation generated by the equation generating unit is reached.
REFERENCES:
patent: 5313398 (1994-05-01), Rohrer et al.
patent: 5369594 (1994-11-01), Huange et al.
patent: 5442569 (1995-08-01), Osano
patent: 5490278 (1996-02-01), Mochizuki
patent: 5754181 (1998-05-01), Amdursky et al.
patent: 5768160 (1998-06-01), Kakegawa
Eickhoff et al., "Levelized Incomplete LU Factorization and its Application to Large-Scale Circuit Simulation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, Issue 6, pp. 720-727, Jun. 1995.
Mayaram et al., "A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulationts", Digest of Technical Papers from the 1990 IEEE International Conference on Computer-Aided Design, pp. 446-449, Nov. 1990.
Wu et al., "Performance Tuning of a Multiprocessor Sparse Matrix Equation Solver", Proceedings of the Twenty-Eighth Hawaii International Conference on System Sciences, vol. II, pp. 4-13, Jan. 1995.
Simic et al., "Partitioning Strategies within a Distributed Multilevel Logic Simulaotr including Dynamic Repartitioning", Proceedings of the European Design Automation Conference, pp. 96-101, Sep. 1993.
Burch et al., "A new Matrix Solution Technique for General Circuit Simulation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, Issue 2, pp. 225-241, Feb. 1993.
Mayaram et al., "A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit And Device Simulations", pp. 446-449, (1990).
Mayaram et al., "A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit And Device Simulations", pp. 446-449, (1990).
NEC Corporation
Sergent Douglas W.
Stamber Eric W.
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