Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-10-16
2001-05-29
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C702S130000, C714S733000
Reexamination Certificate
active
06239607
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit testing, and more particularly, to a method for estimating the leakage current that should be observed when a properly manufactured integrated circuit is tested.
BACKGROUND OF THE INVENTION
After fabrication, integrated circuits (ICs) are routinely tested to determine if the circuits are free of defects. The tester “exercises” the integrated circuit by applying various combinations of signals to the inputs of the IC while observing the outputs generated by these test signals. Each set of input signals is typically referred to as a “test vector”.
One method for detecting defects in integrated circuits is to measure the current drawn from the power source when each test vector is applied to the IC. The current drawn from the power source after the test vector has been applied and held for a sufficient period of time for the IC to have completed any switching caused by the test vector is referred to as the quiescent, or leakage, current and denoted I
DDQ
. In prior art testing systems, an IC having a measured I
DDQ
that is greater than a predetermined threshold, independent of the test vector, is rejected.
The use of a single current threshold as a pass/fail limit for I
DDQ
tests is proving to be a poor technique as CMOS process geometries shrink to the realm where normal I
DDQ
values are dominated by leakage currents, which can be significantly larger than some, or most, defect currents. These leakage currents are due to sub-threshold leakage mechanisms and reverse biased junction leakage mechanisms, although the relative contribution of the latter is becoming smaller and smaller. Both of these mechanisms are characterized by being state-dependent. Hence, an IC will pass a test based on a set of I
DDQ
test vectors only if the single pass/fail threshold is set high enough to account for the state with the most leakage.
If the threshold is set too high, chips with defects that are active in one of the test states that selects a portion of the IC with naturally lower leakage will still pass the I
DDQ
test, leading to the shipment of defective ICs. If on the other hand, the threshold is set low enough to achieve reasonable defect screening, the threshold will be below the minimum current for some ICs, resulting in excessive yield loss by rejecting good ICs.
This problem is further exacerbated by changes in leakage current which occur as the IC fabrication process undergoes normal drift. There is always a range of allowable channel lengths (Leff), and ICs produced with small values of Leff have much higher leakage than those with a longer Leff. This makes it very difficult, if not impossible, to have a single threshold which will work adequately for any given IC across the range of normal process variations.
In principle, the above-described problems can be overcome by utilizing a different threshold value for each test vector. These thresholds would reflect the different I
DDQ
currents that arise from the different states induced by each test vector. The exact value of the individual current thresholds could be established by characterizing ICs that are known to be defect-free from other tests. However, this approach assumes that sufficient good ICs have been produced and that the process does not drift with time.
In principle, detailed simulations can also determine the threshold values. For example, the chip can be simulated using SPICE for each possible test vector. The computational time for providing such a simulation is prohibitive. Alternatively, precharacterized cell information for each standard cell in the chip can be generated using a logic simulator. The leakage currents of the cells would be characterized in detail using SPICE, and this information could then be combined with the circuit state information from logic simulation to calculate an expected value for I
DDQ
. For a typical standard cell library, this approach requires a large amount of characterization data to be stored. Further, the method suffers from a lack of flexibility in being able to adjust estimates based on possible process shifts as well as requiring additional characterization of any custom cells.
Broadly, it is the object of the present invention to provide an improved method for estimating the leakage currents for various test vectors.
It is a further object of the present invention to provide a method for estimating leakage current that does not require detailed SPICE simulations of the entire integrated circuit.
It is a still further object of the present invention to provide a method for estimating the leakage currents that does not require detailed leakage current data to be stored for all of the standard cells in a design library.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
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Randal E. Bryant—“A Switch-Level Model and Simulator for MOS Digital Systems”, IEEE Transactions on Computers, vol. C-33, No. 2, Feb. 1984; pp. 160-177.
P. C. Maxwell and J. R. Rearick, Integrated Circuit Business Division, Hewlett-Packard Company; A Simulation-Based Method for Estimating Defect-Free IDDQ; IEEE International Workshop on IDDQ Testing, Nov. 5-6, 1997, Washington, D.C.
Maxwell Peter
Rearick Jeff
Agilent Technologie,s Inc.
Brown Glenn W.
Hamdan Wasseem H.
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