Simulation and timing control for hardware accelerated...

Details Simulation and timing control for hardware accelerated... Simulation and timing control for hardware accelerated...

2007-08-14

2007-08-14

Rodriguez, Paul (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S017000, C703S021000, C703S027000

Reexamination Certificate

active

10247186

ABSTRACT:
A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.

REFERENCES:
patent: 6134516 (2000-10-01), Wang et al.
patent: 6175946 (2001-01-01), Ly et al.
patent: 6785873 (2004-08-01), Tseng

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