Simplified method for limiting clock pulse width

Details Simplified method for limiting clock pulse width Simplified method for limiting clock pulse width

2007-07-10

2007-07-10

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S165000, C327S175000, C327S176000

Reexamination Certificate

active

10692416

ABSTRACT:
The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pulses are sent through a block delay module that incorporates a series of delay sub-blocks that disconnect and reset in accordance with a pre-programmed total delay time. The conditioned clock pulse is resent through a node to the correction block and leak detector where it is reevaluated. If the pulse is acceptable, it is sent to the clock output. If the pulse is found unacceptable, it is recycled again. A high low clock pulse shuttle determines and alters the high or low state of the clock pulse to ensure a correct output to downstream dependent devices.

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