Simplified fabrication method for high-performance FET

Metal working – Method of mechanical manufacture – Assembling or joining

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29576E, 29580, 29591, 148171, 148175, 357 15, H01L 2120

Patent

active

043251811

ABSTRACT:
A method for making reproducible FET's with gate dimensions in the submiceter range, reduced source-gate channel resistance, and reduced gate and source contact resistances comprising forming, in order, on a semi-insulating substrate, of GaAs, an N-type GaAs layer, an (N+) GaAs layer and an (N++) Ge layer, using a photolith process with a mask to form the gate channel region therein, forming a refractory metal layer covering the whole top of the device, forming a gold layer on the refractory metal, using a photolith method with a common mask and etch process to cut the gate, source and drain electrodes to their desired sizes and using a plasma etch process to cut away, except for a stalk supporting the gate Au electrode, the remaining refractory metal from a portion of the gate channel lying between the gate and source electrode region and lying between the gate and drain electrode region.

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