Simplified delay testing for LSI circuit faults

Details Simplified delay testing for LSI circuit faults Simplified delay testing for LSI circuit faults

1985-12-20

1987-06-09

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Plural, automatically sequential tests

371 27, G01R 3128

Patent

active

046723072

ABSTRACT:
Thorough delay testing of a combinational logic circuit is accomplished by changing only one input at a time (a single transition), and checking the output at a predetermined short time later, and arrangements are disclosed for systematically applying to the inputs of a combinational logic circuit all possible single transitions of the binary input signals. One economical test circuit uses a conventional binary counter and an associated ring counter to generate the test signals, in addition to input switching circuits or multiplexers for steering data to the logic to be tested and control circuitry to control the test process.

REFERENCES:
patent: 3919637 (1975-11-01), Earp
patent: 3988670 (1976-10-01), Gariazzo
patent: 4216539 (1980-08-01), Raymond et al.
patent: 4357703 (1982-11-01), Van Brunt
patent: 4435806 (1984-03-01), Segers et al.
"Bit Pattern Generation Suitable for Use with Magnetic Bubble Testing", by Choy, IBM Tech. Dis. Bull., 4/78, vol. 20, #11B, pp. 4926-4927.
"AT LAST!" by Data Test Corp., Concord, CA, 4/1/71.

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