1980-05-27
1983-10-25
Larkins, William D.
357 22, 357 48, 357 52, 357 89, H01L 2704
Patent
active
044122381
ABSTRACT:
In a monolithic semiconductor integrated circuit, conventional bipolar transistors are fabricated along with thin ion implanted junction field effect transistors, to create BIFET structures. After the conventional isolation diffusion, the surface oxide is stripped off and the semiconductor wafer ion implanted with slow diffusing impurities of a conductivity type, the same as the undiffused surface material. Then the bipolar transistors, along with the junction field effect transistors, are fabricated using conventional oxide masked diffusion processes. The field effect device sources and drains employ the base diffusions of the bipolar transistors while the gate contact is achieved with an emitter diffusion. The field effect device channels are formed at a depth substantially greater than that of the impurities deposited in the original ion implant. If desired, an ion implanted top gate can be established over the channel. The wafer is then annealed and processed in accordance with conventional techniques. Since the original ion implant covers the entire surface of the circuit, it will act as a field inversion prevention layer thus, improving the circuit reliability. The field effect devices can be fabricated with one less masking step when compared with the prior processes.
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Electronic Design, Jan. 4, 1978, pp. 104-111.
Hollins Brian E.
Khadder Wadie N.
Wang Jia T.
Larkins William D.
National Semiconductor Corporation
Schulte Neil B.
Winters Paul J.
Woodward Gail W.
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