Simplified architecture for defuzzification integrated circuit (

Details Simplified architecture for defuzzification integrated circuit ( Simplified architecture for defuzzification integrated circuit (

1996-07-08

1998-12-22

Dorvil, Richemond

395 51, G06G 700

Patent

active

058527087

ABSTRACT:
A digital defuzzification processor implemented as integrated circuits (ICs). The defuzzification IC processor includes an input port for receiving a plurality of input values and a corresponding set of specific weight and an effective area for each of the input values. The defuzzification IC processor further includes a multiplier for multiplying each of the input values to the corresponding specific weight for generating a plurality of partial-input-weighted-specific-weight, the multiplier further multiplying the each of the input values to the corresponding effective area for generating a plurality of partial-input-weighted-effective-area. The defuzzification IC processor further includes an accumulator for adding each of the plurality of partial input-weighted-specific-weight for generating a summed-input-weighted specific-weight, the accumulator further adding each of the plurality of partial-input-weighted-effective-area for generating a summed-input weighted-effective-area. The defuzzification IC processor further includes a divider for dividing the summed-input-weighted-specific-weight by the summed-input-weighted-effective-area for generating a crisp output.

REFERENCES:
patent: 4837725 (1989-06-01), Yamakawa
patent: 4875184 (1989-10-01), Yamakawa
patent: 5131071 (1992-07-01), Tsutsumi et al.
IEEE International Conference on Fuzzy Systems. Pfluger et al., "A defuzzyfication strategy for a fuzzy logic controller emplying prohibitive infromation in command formulation";pp. 717-723, Mar. 1992.
IEEE Transactions on systems, Man, and Cybernetics. Lee, "Fuzzy Logic in Control Systems: Fuzzy Logic Controller Part II"; p. 419-435, Apr. 1990.

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