Simple planarized trench isolation and field oxide formation usi

Details Simple planarized trench isolation and field oxide formation usi Simple planarized trench isolation and field oxide formation usi

1994-04-29

1995-05-02

Fourson, George

Fishing, trapping, and vermin destroying

437924, 437984, H01L 21311, H01L 2176

Patent

active

054119138

ABSTRACT:
A device isolation scheme that is particularly suited to the fabrication of high density, high performance CMOS, bipolar, or BiCMOS devices, and overcomes many of the problems associated with existing isolation methods. Photolithographic techniques are used to define active regions on a substrate. Using the photoresist as a mask for the active regions, the silicon in the inactive regions is etched. A pad oxide layer and nitride layer are then formed on the substrate. A layer of oxide is then deposited and photolithographic techniques are again used to define the locations for desired trench structures. After removal of the remaining photoresist, deep trenches are etched in the silicon substrate. An oxidation step is then carried out to provide a layer of oxide lining the trenches, followed by deposition of a layer of poly-silicon over the substrate, filling the trenches. The poly-silicon layer is etched back, removing it from the tops of the trenches and the field regions, and leaving a poly-silicon spacer on the sides of those portions of the previously deposited oxide layer which cover the active regions. The spacers are used to align a photoresist mask which is used to etch away the oxide layer on top of the active regions. The spacers are then removed while keeping the photoresist mask intact, thereby protecting the poly-silicon on top of the trenches. The photoresist mask is then removed and the poly-silicon on top of each trench is oxidized to cap the trench. The result is a highly planar surface in which active regions are separated by field oxide or poly-silicon filled trenches.

REFERENCES:
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patent: 5294296 (1994-03-01), Yoon et al.
Kurosawa et al., A New Bird's-Beak Free Field Isolation Technology for VLSI Devices, International Electron Devices Meeting, Dig. Tech, Paper, pp. 384-387 (1981).
Rung et al., Deep Trench Isolated CMOS Devices, International Electron Devices meeting, Digest Technical Paper, pp. 237-240 (1982).
Katsumata et al., Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage, ESSDERC, pp. 133-136 (Sep. 1993).
Lutze et al., Electrical Limitations of Advanced LOCOS Isolation for Deep Submicrometer CMOS, IEEE Transactions on Electron Devices, vol. 38, No. 2, pp. 242-245 (Feb., 1991).
Poon et al., A Trench Isolation Process for BiCMOS Circuits, IEE Bipolar Circuits and Technology Meeting 3.3, pp. 45-48 (1993).

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