Simple bus and interface system for consumer digital equipment

Details Simple bus and interface system for consumer digital equipment Simple bus and interface system for consumer digital equipment

1997-11-24

1998-11-24

Peeso, Thomas

39520032, G06F 16153

Patent

active

058419870

DESCRIPTION:

BRIEF SUMMARY
This invention relates to a bus interface system/apparatus for coupling audio, video and data processing systems, and in particular to coupling digital signals for digital recording and reproduction.


BACKGROUND OF THE INVENTION

It is known in the audio/video electronics arts to interconnect a variety of consumer electronic processing devices on a bus structure, so that signal available at one device may be utilized by another device connected on the bus. For example audio/video signal available from a television receiver may be applied to a video cassette recorder for storage, or the audio from a television receiver may be applied to a component stereo system for reproduction etc. Examples of this type of audio/video interconnect systems may be found in U.S. Pat. Nos. 4,575,759; 4,581,664; 4,647,973; and 4,581,645.
The signals distributed in these analog bus systems are relatively self contained. That is they include all the timing information necessary for the respective devices connected to the bus to decode the respective signals.
Currently there are a number of compressed audio and video transmission systems, such as the Grand Alliance HDTV system proposed for terrestrial high definition television broadcasting, or the DirecTV.TM. system which currently broadcasts compressed NTSC signal via satellite. Both systems transmit program material in transport packets, and transport packets for different programs and/or program components may be time division multiplexed in a common frequency band. Respective packets undergo noise detection/correction encoding prior to transmission and after reception, and the transport packets are thereafter reconstituted in a receiver. Recording apparatus (e.g. VCR or video disc) and authoring apparatus (e.g. cameras or camcorders) for compressed signals, on the other hand, may process the compressed signals in the same packet format, however they may not require the same noise processing. As a consequence the conveyance of signal between processing components is most conveniently effected in packet form coupled via a bus. Processing components are coupled to the bus by bus interfaces which may provide bidirectional coupling to or from each processing component. The bus interfaces are coupled to a pair of control lines included in the bus which provides control communication from a master controller.
A simplified method for inter connection is required which eliminates the requirement for a master controller to be coupled via bus control conductors to each bus interface. Such a simplified inter connection method may provide automatic coupling of signal sources to signal destinations, and in addition may prevent two sources utilizing the same bus conductor. The simplified inter connection method may utilize a single pair of bus conductors.


SUMMARY OF THE INVENTION

An apparatus for controllably coupling a source of a packetized signal to a data bus. The apparatus comprises an indicia generator controllably coupled to the source and receiving therefrom the packetized signal. A switching matrix is controlled responsive to the indicia generator for receiving therefrom the packetized signal for coupling to the data bus. In responsive to the controllable coupling from the source, the indicia generator adds an indicia to the packetized signal and enables the switching matrix for coupling the packetized signal and indicia to the data bus.


BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the following drawings wherein;
FIG. 1 is a block diagram of an inventive embodiment of a daisy chain connection of bus hardware including a number of bus/device interfaces; and
FIG. 2 is a block diagram of a portion of one of the bus interfaces of FIG. 1; and
FIGS. 3A and 3B are a first system block diagram illustrating a receiver coupled via a data bus to a source of timing pertubation and and an inventive superpacket restoration block.
FIG. 4A is a waveform and pictorial representation of bus superpackets according to a first arrangement, and
FIG. 4B illu

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