Similarity-extraction force-oriented floor planner

Details Similarity-extraction force-oriented floor planner Similarity-extraction force-oriented floor planner

1994-01-13

1996-04-09

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, H01L 2177

Patent

active

055067883

ABSTRACT:
A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix. The random logic cells are also iteratively sorted according to connectivety requirements of the integrated circuit and are placed over the data path cells as a provisional overlay of the random logic cells, which are then fitted into any open spaces of the cell-space matrix, and are then inserted into either new rows or new columns of the matrix according to a shape-measuring of the overlay of random logic cells.

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M. Hirsch, D. Siewiorek, "Automatically Extracting Structure From A Logical Design", IEEE Proc. of Int. Cof. on CAD, 1988, pp. 456-459.
G. Odawanre, T. Haraide, O. Nishina, "Partitioning and Placement Technique for CMOS Gate Array", IEEE Transactions, May 1987, vol. CAD6, No. 3, pp. 335-363.

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