SIMD addition circuit

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S710000

Reexamination Certificate

active

10283246

ABSTRACT:
A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a distinct data path through the adder. For each set of numbers, the system further includes a logic gate for inhibiting a carry path, from each portion of the adder corresponding to each carry path, to a next adjacent carry path. The system isolates two or more contiguous data paths through the fixed-width adder corresponding to each of the two or more sets of two binary numbers. The invention prevents unwanted signals from crossing summing lane boundaries in different processing modes. The same adder logic can thus be used for each processing mode by varying the combination of mode select control signals.

REFERENCES:
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4768160 (1988-08-01), Yokoyama
patent: 5189636 (1993-02-01), Patti et al.
patent: 5278783 (1994-01-01), Edmondson
patent: 5327369 (1994-07-01), Ashkenazi
patent: 5390135 (1995-02-01), Lee et al.
patent: 5757685 (1998-05-01), Ohuchi
patent: 5883824 (1999-03-01), Lee et al.
patent: 6449629 (2002-09-01), Morgan
patent: 6519622 (2003-02-01), Knowles
patent: 2 342 193 (2000-04-01), None
Simon Knowles, “A Family of Adders”,IEEE, pp. 30-37, 1999.

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