Silicon wafers and method of fabricating the same

Details Silicon wafers and method of fabricating the same Silicon wafers and method of fabricating the same

2007-07-10

2007-07-10

Wilczewski, M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

With specified dopant

Deep level dopant

C257S617000, C257SE21321

Reexamination Certificate

active

10699438

ABSTRACT:
By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.

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Office Action issued by Korean Intellectual Property Office dated May 27, 2005.
Office action from the Chinese Patent Office for Chinese Application No. 200410005410.1, corresponding to U.S. Appl. No. 10/699,438.
English translation of the office action for Chinese Application No. 2004 10005410.1.

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