Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth with a subsequent step of heat treating...
Reexamination Certificate
2000-09-22
2003-12-16
Utech, Benjamin L. (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth with a subsequent step of heat treating...
C117S011000, C117S013000, C438S795000, C432S001000
Reexamination Certificate
active
06663708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit oriented silicon wafer sliced out of a silicon ingot manufactured by a Czochralski method (hereinafter called “CZ method”), and to a manufacturing method of the silicon wafer. The present invention further relates to a method for heat treating such a semiconductor integrated circuit oriented silicon wafer, so as to render such a silicon wafer to exhibit an intrinsic gettering effect (hereinafter called “IG effect”).
2. Description of the Related Art
Recently, causes of deterioration of yields in processes for manufacturing semiconductor integrated circuits include existence of: micro defects of oxygen precipitations which lead to nuclei of oxidation induced stacking faults (hereinafter called “OSF's”); crystal originated particles (hereinafter called “COP's”); and an interstitial-type large dislocation (hereinafter called “L/D”). Micro defects as nuclei of OSF's are introduced into a silicon ingot during crystal growth, and actualize such as in an oxidation process on manufacturing semiconductor devices, leading to malfunctions such as increase of leakage current of fabricated devices. Meantime, cleaning mirror-polished silicon wafers by a mixed solution of ammonia and hydrogen peroxide leads to formation of pits on the wafer surface, and such pits are detected as particles similarly to real or intrinsic particles. Such pits are called COP's, to distinguish them from real particles. COP's which are pits on a wafer surface cause deterioration of electric characteristics such as a time dependent dielectric breakdown (TDDB) characteristic and a time zero dielectric breakdown (TZDB) characteristic. Further, existence of COP's in a wafer surface causes physical steps during a wiring process of devices, and these steps cause wire breakage to thereby reduce the yield of products. On the other hand, an L/D is called a dislocation cluster, or a dislocation pit since a pit is formed when a silicon wafer having this defect is immersed in a selective etching solution containing hydrofluoric acid as a main ingredient. Such an L/D also causes deterioration of electric characteristics such as a leak characteristic and an isolation characteristic.
From the above, it is required to reduce OSF's, COP's and L/D's from a silicon wafer to be used for manufacturing a semiconductor integrated circuit.
As a method for reducing such OSF's and COP's, there has been conventionally disclosed one for heat treating a silicon wafer in an atmosphere of 100% hydrogen or in an atmosphere of mixed hydrogen and argon at temperatures in a range of 1,200° C. to a melting point of silicon, making use of an apparatus capable of rapidly heating and rapidly cooling the silicon wafer (Japanese Patent Application Laid-Open No. HEI-10-326790). By this method, the number of COP's of 0.12 &mgr;m or greater per 8-inch diameter wafer can be reduced to 50 or less, to thereby improve the yield having been deteriorated due to the time zero dielectric breakdown characteristic.
In the conventional method, however, there is used a silicon wafer in which the number of COP's of 0.12 &mgr;m or greater on the whole surface of an 8-inch diameter wafer is 300 or more before heat treatment, problematically resulting in that it will be extremely difficult to reduce the number of COP's down to substantially zero over the whole surface of the wafer and that the wafer is susceptible to contamination such as Fe due to the high-temperature heat treatment exceeding 1,250° C. in a reductive atmosphere. Further, the heat treatment at temperatures higher than 1,150° C. by the apparatus capable of rapidly heating and rapidly cooling tends to problematically cause slip which is a kind of crystal defect. In addition, rapid heating leads to suppression of oxygen precipitation nuclei to be introduced upon pulling up, resulting in that precipitation of such nuclei in a device process becomes insufficient and no gettering effects can be expected, so that the removing ability of the wafer for removing contaminous impurities due to metal contamination is defectively lowered.
Meanwhile, there has been conventionally disclosed a defect-free silicon wafer free of OSF's, COP's and L/D's, in Japanese Patent Application Laid-Open No. HEI-11-1393. This defect-free silicon wafer is one sliced out from a single silicon crystal ingot comprising a perfect domain [P] supposed to be free of agglomerates of vacancy point defects and free of agglomerates of interstitial silicon point defects within the ingot. The perfect domain [P] exists between an interstitial silicon point defect dominant domain [I] and a vacancy point defect dominant domain [V] within the single silicon crystal ingot. The silicon wafer comprising the perfect domain [P] is formed by determining a value of V/G (mm
2
/minute ° C.) such that OSF's generated in a ring shape during a thermal oxidization treatment disappears at the center of the wafer, in which V (mm/minute) is a pulling-up speed of the ingot, and G (° C./minute) is a vertical temperature gradient of the ingot near the interface between a silicon melt and the ingot.
The silicon wafer sliced out from an ingot comprising the perfect domain [P] is free of OSF's, COP's and L/D's. However, oxygen precipitation is not necessarily caused within the wafer by the heat treatment in a device manufacturing process, leading to a possibility of an insufficient IG effect. Some semiconductor device manufacturers may demand silicon wafers which are free of OSF's, COP's and L/D's but have abilities for gettering metal contamination caused in the device process. Metal contamination of wafers having insufficient IG abilities in the device process leads to junction leakage, and to occurrence of malfunctions of devices due to a trap level of metal impurities.
Further, there has been proposed a heat treatment method for exhibiting an IG effect (Japanese Patent Application Laid-Open No. HEI-8-45945), comprising the steps of: holding a silicon wafer just ground and polished after sliced out from a single silicon crystal ingot at 500 to 800° C. for 0.5 to 20 hours, to thereby introduce oxygen precipitation nuclei into the wafer; rapidly heating the silicon wafer including the oxygen precipitation nuclei from a room temperature to temperatures of 800-1,000° C. and holding the wafer for 0.5 to 20 minutes; leaving the silicon wafer rapidly heated and held for 0.5 to 20 minutes, down to a room temperature; and heating the thus cooled silicon wafer from temperatures of 500 to 700° C. up to temperatures of 800 to 1,100° C. at a rate of 2 to 10° C./minute, and holding the silicon wafer at this temperature for 2 to 48 hours.
In this treating method, at the surface as well as the interior of the wafer rapidly heated under the aforementioned temperature condition, the concentration of interstitial silicon atoms temporarily becomes lower than a thermal equilibrium concentration, leading to a depleted condition of interstitial silicon atoms to thereby provide an environment where oxygen precipitation nuclei tend to stably grow. Simultaneously, generation of interstitial silicon atoms are caused at the wafer surface so as to fill the depleted interstitial silicon atoms into a stable condition, so that the generated interstitial silicon atoms start to diffuse into the interior of the wafer. The area near the wafer surface which has been in the depleted condition of interstitial silicon atoms immediately falls into a saturated condition so that oxygen precipitation nuclei start to disappear. However, it will take some period of time for interstitial silicon atoms grown in the wafer surface to diffuse into the wafer interior. Thus, the deeper the distance from the wafer surface into the wafer interior, the longer the period of time over which an environment for easy growth of oxygen p
Furukawa Jun
Furuya Hisashi
Koya Hiroshi
Morita Etsuro
Nakada Yoshinobu
Mitsubishi Materials Silicon Corporation
Reed Smith LLP
Song Matthew
Utech Benjamin L.
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