Silicon wafer and its manufacturing method

Details Silicon wafer and its manufacturing method Silicon wafer and its manufacturing method

2011-05-03

2011-05-03

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

With specified impurity concentration gradient

C257S620000, C257SE21122, C257SE21077, C438S502000, C438S522000, C438S530000, C438S633000

Reexamination Certificate

active

07936051

ABSTRACT:
A silicon wafer which achieves a gettering effect without occurrence of slip dislocations is provided, and the silicon wafer is subject to heat treatment after slicing from a silicon monocrystal ingot so that a layer which has zero light scattering defects according to the 90° light scattering method is formed in a region at a depth from the wafer surface of 25 μm or more but less than 100 μm, and a layer which has a light scattering defect density of 1×108/cm3or more according to the 90° light scattering method is formed in a region at a depth of 100 μm from the wafer surface.

REFERENCES:
patent: 2005/0229842 (2005-10-01), Umeno et al.
patent: 2006/0291832 (2006-12-01), Ito
patent: 2003-055088 (2003-02-01), None
patent: 2003-059932 (2003-02-01), None
patent: 2006-310690 (2006-11-01), None
patent: 2008166517 (2008-07-01), None
patent: 1019990077707 (1999-10-01), None
English Language Abstract of JP 2006-310690 A.
U.S. Appl. No. 12/035,588 to Toshiaki Ono et al., filed Feb. 22, 2008, entitled “Soi Wafer and Manufacturing Method Thereof”.
Korean Office Action dated Mar. 25, 2010 that issued with respect to patent family member Korean Patent Application No. 10-2008-0013377, along with a partial English language translation.

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