Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state
Reexamination Certificate
2000-10-23
2002-08-06
Hiteshew, Felisa (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
C117S090000, C117S092000, C428S212000
Reexamination Certificate
active
06428619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of heat treating a silicon wafer prepared by a Czochralski method (hereinafter, referred to as “a CZ method”) to be used for manufacturing a semiconductor integrated circuit, a wafer to be used in such a method, and a heat-treated wafer obtained by such a heat treatment method.
2. Description of the Related Art
Recently, causes of deterioration of yields in processes for manufacturing semiconductor integrated circuits include existence of: micro defects of oxygen precipitations which lead to nuclei of oxidation induced stacking faults (hereinafter referred to as “OSF's”); crystal-originated particles (hereinafter referred to as “COP's”); and an interstitial-type large dislocation (hereinafter referred to as “L/D”). Micro defects as nuclei of OSF's are introduced into a silicon ingot during crystal growth, and actualize such as in an oxidation process on manufacturing semiconductor devices, leading to malfunctions such as increase of leakage current of fabricated devices. Meantime, cleaning mirror-polished silicon wafers by a mixed solution of ammonia and hydrogen peroxide leads to formation of pits on the wafer surface, and such pits are detected as particles similarly to real or intrinsic particles. Such pits are referred to as COP's, to distinguish them from real particles. COP's which are pits on a wafer surface cause deterioration of electric characteristics such as a time dependent dielectric breakdown (TDDB) characteristic and a time zero dielectric breakdown (TZDB) characteristic. Further, existence of COP's in a wafer surface causes physical steps during a wiring process of devices, and these steps cause wire breakage. In addition, it causes troubles such as leakage on a device separating portion, so that the yield of products is reduced.
On the other hand, an L/D is called a dislocation cluster, or a dislocation pit since a pit is formed when a silicon wafer having this defect is immersed in a selective etching solution containing hydrofluoric acid as a main ingredient. Such an L/D also causes deterioration of electric characteristics such as a leak characteristic and an isolation characteristic.
From the above, it is required to reduce OSF's, COP's and L/Ds from a silicon wafer to be used for manufacturing a semiconductor integrated circuit.
As a method for reducing such OSF's and L/Ds, there has been conventionally disclosed a defect-free silicon wafer free of OSF's, COP's and L/Ds in Japanese Patent Application Laid-Open Nos. HEI 8-330316 (1996) and HEI-11-1393 (1999).
In the method disclosed in Japanese Patent Application Laid-Open No. HEI 8-330316 (1996), a silicon monocrystal is grown at a lower speed so that OSF's being formed like a ring is disappeared from a center of the wafer and L/Ds are removed from the whole surface of the wafer, while OSF to be caused like a ring at the time of heat-treating the silicon monocrystal as a silicon wafer.
However, the range of speed for pulling a silicon monocrystal and the range of temperature gradation in the crystal in the axial direction for making a non-defective silicon monocrystal by the method disclosed in the above reference are confined in comparatively narrow limits, respectively. Manufacturing the non-defective silicon monocrystal will become more difficult with increasing diameter of a silicon monocrystal being pulled. In some cases, OSF's may be occurred as a mass on the central part of the wafer but not as a ring by the variations in the pulling speed or the like. The OSF's lead to deterioration of the leak characteristic as described above, so that the improvements on the process of manufacturing a silicon monocrystal have been demanded.
The method disclosed in Japanese Patent Application Laid-Open No. HEI-11-1393 (1999) including the step of pulling a single silicon crystal ingot comprising a perfect domain [P] from a silicon melt, where the perfect domain [P] is supposed to be free of agglomerates of vacancy point defects and free of agglomerates of interstitial silicon point defects within the ingot. The silicon wafer sliced out from the ingot consists of the perfect domain region [P]. The perfect domain [P] exists between an interstitial silicon point defect dominant domain [I] and a vacancy point defect dominant domain [V] within the single silicon crystal ingot. The silicon wafer comprising the perfect domain [P] is formed by determining a value of V/G (mm
2
/minute °C.) such that OSF's generated in a ring shape during a thermal oxidization treatment disappears at the center of the wafer, in which V (mm/minute) is a pulling-up speed of the ingot, and G (°C./minute) is a vertical temperature gradient of the ingot near the interface between a silicon melt and the ingot.
On the other hand, some semiconductor device manufacturers may demand silicon wafers which are free of OSF's, COP's and L/Ds but have abilities for gettering metal contamination caused in the device process. Metal contamination of wafers having insufficient gettering abilities in the device process leads to junction leakage, and to occurrence of malfunctions of devices due to a trap level of metal impurities. To solve this problem, there has been demanded a silicon wafer that exerts the effect of intrinsic gettering (IG) by a heat treatment during the device process of the device maker.
The silicon wafer sliced out from the ingot comprising the perfect domain [P] described above is free of OSF's, COP's and L/Ds. However, oxygen precipitation is not necessarily caused within the wafer by the heat treatment in a device manufacturing process, leading to the disadvantage of causing an insufficient IG effect.
Conventionally, the step of treating a silicon wafer for making full use of the capabilities of. IG effect of the silicon wafer during the device process may be of making defections in the wafer in advance or adding impurities intentionally in advance. In the silicon wafer treated by such a step, contaminants generated by the subsequent steps are absorbed around the preformed defections of the wafer. Therefore, we can prevent the generation of any defection or contamination on an area in proximity to the wafer's surface on which a device is to be formed.
On the other hand, there is a tendency to decrease a heat treatment temperature to a temperature of 1,000° C. or less in the device process because of increasing the packing density of device in recent years. Therefore, it is strongly desirable to perform the IG treatment at a low temperature as a pretreatment in the device process.
Further, there has been proposed a heat treatment method for exhibiting an IG effect (Japanese Patent Application Laid-Open No. HEI-8-45945 (1996)), comprising the steps of: holding a silicon wafer just ground and polished after sliced out from a single silicon crystal ingot at 500 to 800° C. for 0.5 to 20 hours, to thereby introduce oxygen precipitation nuclei into the wafer; rapidly heating the silicon wafer including the oxygen precipitation nuclei from a room temperature to temperatures of 800-1,000° C. and holding the wafer for 0.5 to 20 minutes; leaving the silicon wafer rapidly heated and held for 0.5 to 20 minutes, down to a room temperature; and heating the thus cooled silicon wafer from temperatures of 500 to 700° C. up to temperatures of 800 to 1,100° C. at a rate of 2 to 10° C./minute, and holding the silicon wafer at this temperature for 2 to 48 hours.
In this treating method, at the surface as well as the interior of the wafer rapidly heated under the aforementioned temperature condition, the concentration of interstitial silicon atoms temporarily becomes lower than a thermal equilibrium concentration, leading to a depleted condition of interstitial silicon atoms to thereby provide an environment where oxygen precipitation nuclei tend to stably grow. Simultaneously, generati
Furuya Hisashi
Koya Hiroshi
Muroi Yukio
Shiota Takaaki
Suzuki Yoji
Mitsubishi Materials Silicon Corporation
Reed Smith LLP
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