Silicon wafer

Details Silicon wafer Silicon wafer

2000-10-24

2003-07-29

Lam, Cathy (Department: 1775)

Stock material or miscellaneous articles

Circular sheet or circular blank

C428S446000, C117S931000, C117S932000, C423S348000

Reexamination Certificate

active

06599603

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a silicon wafer wherein crystal defects generated inside a silicon single crystal in pulling the crystal by Czochralski method (CZ method) are easily eliminated by heat treatment after pulling the crystal.
BACKGROUND ART
As a wafer for fabrication of a device such as a semiconductor integrated circuit, a silicon single crystal wafer grown by Czochralski method (CZ method) is mainly used. If crystal defects are present in such a silicon single crystal wafer, pattern failure is caused when a semiconductor device is fabricated. Particularly, the pattern width of devices which is highly integrated in recent years is very fine as 0.3 &mgr;m or less. Accordingly, even small crystal defects as 0.1 &mgr;m may cause defects such as pattern failures in the device, and may remarkably lower a yield and characteristics of the device. Accordingly, a size and density of the crystal defects in the silicon single crystal wafer have to be decreased as thoroughly as possible.
Recently, it has been reported that the crystal defect, what is called Grown-in defects incorporated during growth of the crystal are found in the silicon single crystal grown by CZ method. The main cause of generation of such crystal defects is considered to be a cluster of atomic vacancies which are aggregated during manufacture of single crystal or an oxide precipitate which is an agglomerate of oxygen atoms getting in from a quartz crucible. When these crystal defects are present in the surface portion in which a device is fabricated, they come to harmful defect to degrade characteristics of the device. Accordingly, it is desirable to manufacture a silicon wafer having denuded zone (DZ) of sufficient depth in the surface portion with reduced such crystal defects.
In the above-described grown-in defect, it is known that a shape of grown-in defect as a void type defect has a structure of connecting with a few voids on the basis of octahedron, a size of grown-in defect is about 100-300 nm, and the surface of grown-in defect is covered with oxide film (M. Kato, T. Yoshida, Y. Ikeda, and Y. Kitagawa, Jpn. J. Appl. Phys. 35, 5597, 1996).
FIG.
3
and
FIG. 4
show observation diagrams of a void defect projected on a {110} plane by a transmission electron microscope. It is considered that this defect is formed from aggregating atomic vacancies at a temperature range of close to 1150° C. in manufacturing a single crystal by Czochralski method. When such crystal defects are present in the surface portion (at a depth of 0 to 5 &mgr;m) of the wafer in which a device is fabricated, they come to harmful defects to degrade characteristics of a device. Accordingly, various methods to reduce such defects have been examined.
For example, it is known that the density of the above-described grown-in void defects can be lowered by high temperature heat treatment to a silicon wafer. However, adopting this method to a conventional silicon wafer grown by CZ method, there is a problem that not a few defects are still present in a inner region of from the wafer surface to about 0.3 &mgr;m in depth or more, and a depth of denuded zone becomes shallow. Consequently, a conventional wafer has low flexibility in fabrication of a device.
DISCLOSURE OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned problems, and an object of the present invention is to obtain a silicon wafer, which is suitable for increasing reductional effect of void defects by heat treatment, and expanding denuded zone up to a deeper region.
To solve the above problem, the present invention provides a silicon wafer produced by processing a silicon single crystal ingot pulled by Czochralski method, wherein the silicon wafer includes rod-like void defects and/or plate-like void defects inside the wafer.
As described above, when a silicon single crystal ingot is grown by CZ method, defects inside the ingot are formed in rod-like and/or plate-like shape. As the result of this, a relative ratio of the surface area versus the volume of the defects is higher than that of octahedral defects, and when heat treatment is performed, the defects are reduced up to a deeper region.
In addition, the shape of defects, namely, rod-like and/or plate-like shape in this regard does not mean the shape of void defects such as octahedral or spherical shape included inside a conventional wafer.
For example, in the case of observing the inside of a wafer by a transmission electron microscope, it is regarded as grown-in defect that when an optional rectangle circumscribed a defect image projected on an optional {110} plane is drawn, a maximum value of a ratio between long side length L
1
and short side length L
2
(L
1
/L
2
) is 2.5 or more.
Also, the present invention provides a silicon wafer produced by processing a silicon single crystal ingot grown by Czochralski method, wherein the silicon wafer includes void defects inside the wafer, and a maximum value of a ratio between long side length L
1
and short side length L
2
(L
1
/L
2
) in an optional rectangle circumscribed the void defect image projected on an optional {110} plane is 2.5 or more.
As described above, the wafer whose maximum value of a ratio between long side length L
1
and short side length L
2
(L
1
/L
2
) in an optional rectangle circumscribed a void defect image projected on an optional {110} plane is 2.5 or more is that a relative ratio of the surface area versus the volume of defects is higher than that of octahedral defects, and the defects can be reduced up to a deeper region when heat treatment is performed.
On the other hand, although, the upper limit of the maximum value is not determined in particular, it is supposed to be about 20.
In addition, in order to observe a void defect image projected on an optional {110} plane, using a transmission electron microscope can easily specify a projected plane and correctly observe a defect image.
In this case, it is possible that the above-described single crystal ingot is grown by Czochralski method with doping nitrogen.
In order to form void defects in the aforementioned rod-like and/or plate-like shape, for example, when a silicon single crystal ingot is grown by Czochralski method with doping nitrogen, the shape of grown-in defects can be easily changed octahedral shape into rod-like or plate-like shape.
Also, the present invention provides a silicon wafer wherein the silicon wafer is subjected to heat treatment at a temperature of 1000° C. or more for 10 seconds or more.
As described above, when the wafer including rod-like or plate-like defects is subjected to heat treatment, the void defects, which are present nearby the wafer surface, can be eliminated effectively to a deeper region than a conventional wafer including octahedral defects, and such a silicon wafer can be obtained with high quality. Moreover, since defect eliminating effect by heat treatment is very high, higher defect eliminating effect can be obtained by shorter time heat treatment than a conventional wafer.
In this case, a heat treatment temperature is sufficient for 1000° C. or more, and its upper limit is not determined in particular. However, in physically, the upper limit of the heat treatment temperature is sufficient for the melting point of silicon or less, and in considering practical temperature range in a heat treatment apparatus, it is desirable that the upper limit of the heat treatment temperature is about 1350° C. Also, heat treatment time is sufficient for 10 seconds or more, and its upper limit is not determined in particular. However, in considering productivity, it is desirable that the upper limit of the heat treatment time is about 2 hours.
In this case, it is possible that the silicon wafer wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 &mgr;m after the above-described heat treatment is ½ or less than that of the silicon wafer before the heat treatment. Such a silicon wafer, for example, inclu

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