Silicon wafer

Details Silicon wafer Silicon wafer

2000-09-25

2002-02-19

Jones, Deborah (Department: 1775)

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C428S469000, C428S689000, C148S033000

Reexamination Certificate

active

06348261

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon wafer grown by a Czochralski method (hereinafter called “CZ method”), and more particularly to a silicon wafer to be used for: a memory device such as a DRAM (Dynamic Random Access Memory) as an LSI device, a flash memory, an FRAM (Feroelectric Random Access Memory): a CCD (Charge Coupled Device); and a variety of logic devices, mainly microprocessors.
2. Description of the Related Art
Generally, to fabricate various silicon devices, there has been widely used a CZ silicon wafer which is manufactured by pulling up a silicon single crystal ingot from a silicon melt within a quartz crucible by a CZ method.
In such a CZ wafer, excessive oxygen atoms eluted from the quartz crucible are interstitially caught in the silicon single crystal ingot, and the higher concentration of such interstitial oxygen atoms leads to, for example, oxygen precipitation from the silicon wafer, deterioration of a gate oxide film in a semiconductor integrated circuit, and an increase of a p-n junction leakage current. As such, upon forming semiconductor integrated circuits on the principal plane of the CZ wafer, there are reduced oxygen precipitations near the surface of the wafer by lowering the oxygen concentration of the silicon wafer.
However, it is known that, in a CZ wafer, void defects (D defects) are caused within the crystal due to aggregation of atomic vacancies, and the exposure of such defects at the surface of the wafer results in an occurrence of pits called “COP (Crystal Originated Particle)”. Such a COP is an etch pit having a deep bottom caused by crystals counted as particles by a laser particle counter after cleaning by an SC-1 liquid during an RCA cleaning method. Formation of an oxide film in a wafer surface including such COP's causes deterioration of electric characteristics such as a time dependent dielectric breakdown (TDDB) characteristic, a time zero dielectric breakdown (TZDB) characteristic, and a gate oxide integrity (hereinafter called “GOI”) characteristic; even the concentration of the oxygen precipitations near the wafer surface is low. Further, the existence of COP's in the wafer surface generates a level difference in a wiring process of devices, and this level difference causes breaking of a wire to thereby reduce the yield of products. Moreover, it is known that the existence of COP's causes isolation failure of devices due to the surface-pit caused defects of separated oxide films.
To improve the above points, there is known an epitaxial wafer obtained by forming an epitaxial layer on the surface of a CZ wafer. Such an epitaxial layer catches no oxygen atoms during its growing process, differently from a CZ wafer. Further, in epitaxial wafers, grown-in defects are less which otherwise abundantly exist in CZ wafers, and COP's are covered by an epitaxial layer so that pits like COP's can be expelled from an epitaxial layer surface. Further, a gate oxide film to be obtained by thermally oxidizing a surface of an epitaxial layer is more reliable than that to be obtained by thermally oxidizing a surface of an CZ wafer, thereby enabling improvement of the GOI characteristic.
However, it is becoming apparent that, although the epitaxial layer itself formed on a CZ wafer has lesser grown-in defects and oxygen precipitations, for example, the epitaxial layer may include stacking faults inherent thereto and projections called “mound”, thereby deteriorating the device characteristics more severely than by COP's. On the other hand, upon forming an epitaxial layer on a Cz wafer, it is required to conduct a hydrogen annealing treatment at temperatures from 950° C. to 1,100° C. for several tens of minutes, so as to remove a native oxide at the surface of the CZ wafer in advance. However, this treatment causes dissolution and disappearance of grown-in defects within the CZ wafer to thereby also restrict oxygen precipitation, defectively or problematically resulting in deterioration of a gettering ability of the CZ wafer itself.
Meanwhile, when no epitaxial layers are formed, the aforementioned void defects within a CZ wafer are characteristically found within a ring-like generation domain of “oxidation induced stacking faults (hereinafter called “OSF”)” to be usually found depending on the pulling-up conditions of crystals. As such, crystals including diameter-reduced OSF rings have been recently turned out to be used widely, so as to reduce the ratio of a generation domain of void defects to the whole of a wafer. By adopting such a method, there has been also proposed a low-speed pulled-up crystal which is free of void defects by extremely reducing the pulling-up speed.
However, detailed research of a GOI characteristic and a p-n junction leakage current characteristic of a wafer having a diameter-reduced OSF ring has revealed that the GOI characteristic is considerably deteriorated not only inside an OSF ring but also on the OSF ring, and that the p-n junction leakage current characteristic is also considerably deteriorated on the OSF ring and does not exhibit uniform values at the inside and outside of the OSF ring. Further, it has become apparent that void defects are expelled in a low-speed pulled-up crystal, but dislocation loops are generated in such a crystal, to thereby considerably deteriorate the p-n junction leakage current.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a silicon wafer capable of achieving a higher performance, higher yield and uniformity of characteristics of semiconductor devices comparable to a wafer provided with a pure epitaxial layer, without deteriorating the gettering ability of the silicon wafer.
To this end, in the first aspect of the present invention, a silicon wafer is free of vacancy agglomerates and interstitial agglomerates, wherein the silicon wafer has a defect density of an oxide film of 0.1 piece/cm
2
or less, when the oxide film having a thickness of 5 to 25 nm is formed on the surface of the wafer and a DC voltage of 10 MV/cm is applied via the oxide film for 100 seconds, and wherein the silicon wafer has an in-plane dispersion of 20% or less of a p-n junction leakage current in a p-n junction area of 1 mm
2
or more of a p-n junction portion when the p-n junction portions are formed on the surface of the wafer.
Further, in the second aspect of the present invention, a silicon wafer is free of vacancy agglomerates and interstitial agglomerates, wherein the silicon wafer has a defect density of an oxide film of 0.1 piece/cm
2
or less, when the oxide film having a thickness of 5 to 25 nm is formed on the surface of the wafer and a DC voltage of 10 MV/cm is applied via the oxide film for 100 seconds, and wherein the silicon wafer has in-plane dispersions of 20% or less of both of: a recombination lifetime by a photo conductive decay method; and a generation lifetime measured by a MOS C-t method by forming a MOS capacitor.
In this concern, the basic characteristics of a crystal factor for determining a characteristic of a silicon device is the GOI characteristic and the p-n junction leakage current characteristic. These characteristics can not be satisfied such as when the defect density of an oxide film exceeds 0.1 piece/cm
2
, or when the in-plane dispersion of a p-n junction leakage current in a junction is area greater than 1 mm
2
at the p-n junction portion or the in-plane dispersions of both of a recombination lifetime and a generation lifetime exceeds or exceed 20%. The defect density of an oxide film is preferably 0.06 piece/cm
2
or less, and the in-plane dispersion of a p-n junction leakage current in a junction area greater than 1 mm
2
at the p-n junction portion or the in-plane dispersions of both of a recombination lifetime and a generation lifetime is/are preferably 10% or less.
The present silicon wafers according to the first and second aspects satisfy these characteristics, to thereby guarantee characteristics of various semiconductor devices with h

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