Silicon topography control method

Details Silicon topography control method Silicon topography control method

1993-05-19

1994-10-25

Thomas, Tom

Fishing, trapping, and vermin destroying

437 97, 437 90, 437 31, H01L 21265

Patent

active

053588819

ABSTRACT:
A semiconductor method for establishing a predetermined, constant-depth recess in a semiconductor structure fabricated on the surface of a silicon substrate or wafer. Fabrication includes first growing a thin screen oxide layer on the surface of the wafer. Next, polysilicon is deposited over the screen oxide. Then, windows are defined for ion implantation of buried dopant layers. The window regions are then etched away to the level of the screen oxide. The patterned window resist layer is retained to shield the implant and to enable dopant ions to penetrate the silicon crystal substrate only within defined window regions. At the end of fabrication, the resist pattern is removed and the semiconductor structure is annealed and oxidized.

REFERENCES:
patent: 3909304 (1975-09-01), Cho
patent: 3950188 (1976-04-01), Bower
patent: 4239559 (1980-12-01), Ito
patent: 4717687 (1988-01-01), Verma
patent: 4737468 (1988-04-01), Martin

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