Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-07-25
2006-07-25
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S437000
Reexamination Certificate
active
07081395
ABSTRACT:
A method of forming a strained silicon layer created via a material mis-match with adjacent trench isolation (TI), regions filled with a dielectric layer comprised with either a higher, or lower thermal expansion coefficient than that of silicon, has been developed. Filling of trenches with a dielectric layer comprised with a higher thermal expansion coefficient than that of silicon results in a tensile strain in planar direction and compressive strain in vertical direction, in an adjacent silicon region. Enhanced electron mobility in channel regions of an N channel MOSFET device, and enhanced hole mobility and transit time in an N type base region of a vertical PNP bipolar device, is realized when these elements are formed in the silicon layer under tensile strain. Filling of trenches with a dielectric layer comprised with a lower thermal expansion coefficient than the thermal expansion coefficient of silicon results in a compressive strain in planar directions and tensile strain in vertical directions, in an adjacent silicon region. Enhanced hole mobility in channel regions of an P channel MOSFET device, and enhanced electron mobility and transit time in a P type base region of a vertical NPN bipolar device, is realized when these elements are formed in the silicon layer under compressive strain.
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Chi Min-Hwa
Hu Chenming
Yeo Yee-Chia
Dang Trung
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
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