Silicon single crystal wafer annealing method and equipment and

Details Silicon single crystal wafer annealing method and equipment and Silicon single crystal wafer annealing method and equipment and

1998-03-12

1999-08-03

Kunemund, Robert

Heating

Processes of heating or heater operation

Including preparing or arranging work for heating

432 5, 432 9, 432241, 432253, 432258, 432259, 118500, 118728, 211 4118, 206454, 206832, F27D 312, B05C 1300, B65D 8548

Patent

active

059316624

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention involves an annealing method as well as a manufacturing method whereby a large volume of silicon single crystal wafers are simultaneously and uniformly annealed, and is related to a silicon single crystal wafer annealing method as well as a manufacturing method that uses this annealing method, which enables annealing to be performed uniformly and effectively on large numbers of wafers processed simultaneously using a variety of annealing, to include, for instance, oxygen outward diffusion annealing for forming a denuded zone (DZ) layer, annealing that generates and controls oxygen precipitate-induced bulk micro defect (BMD) for the provision of intrinsic gettering (IG) functions, and annealing that endeavors to enhance device characteristics by eliminating grown-in defects, which give rise to surface crystal originated particles (COP) and internal COP, by stacking up approximately 10 wafers, for example, to form a group, and stacking this group of wafers up vertically with a plurality of wafer groups by inclining each group slightly from the horizontal, and subjecting them to the required annealing in the same furnace.


BACKGROUND ART

Silicon wafers used in MOS ULSI devices are almost all grown via Czochralski (CZ) crystal pulling method. Silicon single crystals grown via this CZ process ordinarily contain around 10.sup.18 atoms/cm.sup.3 of oxygen impurities, and if used as-is in device fabrication processes, the supersaturated oxygen atoms precipitate during processing.
Further, the volume expansion of this oxygen precipitate causes secondary defects such as dislocations and stacking faults. These oxygen precipitates (BMD) and their secondary defects greatly impact the characteristics of a semiconductor device, and when defect occurs on the wafer surface or in the device active layer, it causes increases in leakage current and poor gate oxide integrity (GOI).
Further, grown-in defects introduced during the growth of silicon single crystal using the CZ process were not considered problems in line with the increased integration and downscaling of metal oxide semiconductor (MOS) large scale integration (LSI) up to the 16 megabit dynamic random access memory (16M DRAM) stage. However, because it markedly degrades the GOI characteristics of an MOS capacitor, for 64M DRAM and subsequent devices, the suitability of the near-surface crystallinity of a silicon single crystal substrate will be a major factor in determining device reliability and yield.
Therefore, as a method of improving GOI characteristics during the growth of single crystals via the CZ process, it has been proposed (Kokai No. 2-267195) that a crystal growth rate wherein a crystal is pulled at a slow speed of less than 0.8 mm/min can greatly improve the GOI characteristics of a silicon single crystal substrate.
Further, as a method for reducing grown-in defect in silicon single crystals, it has been proposed (Kokai No. 8-12493) that crystal growth be carried out by setting the cooling rate in the temperature range between 1,150.degree. C. and 1,000.degree. C. to less than 2.0.degree. C./min.
As a separate procedure, it was disclosed in Kokai No. 5-319987 and Kokai No. 5-319988 that grown-in defect introduced during crystal growth can be shrunk and eliminated, and the reliability of a gate oxide layer can be improved by annealing a silicon single crystal ingot at between 1,150.degree. C. and 1,400.degree. C. immediately after it has been pulled via the CZ process.
Further, as a means of wafer annealing, Kokai No. 60-231365, Kokai No. 61-193456, and Kokai No. 61-193458 and others disclosed a method for forming a DZ layer by promoting the outward diffusion of oxygen near a silicon wafer surface layer by annealing a silicon substrate for 5 minutes or longer at temperatures ranging from 950.degree. C. and 1,200.degree. C. in a hydrogen environment or a hydrogen-containing environment.
Meanwhile, heavy metal contaminants typified by iron (Fe), nickel (Ni) and copper (Cu) occur in a high-temperature annealing proc

REFERENCES:
patent: 5219079 (1993-06-01), Nakamura
patent: 5494524 (1996-02-01), Inaba et al.
patent: 5586880 (1996-12-01), Ohsawa
patent: 5688116 (1997-11-01), Kobayashi et al.
patent: 5718574 (1998-02-01), Shimazu
patent: 5746591 (1998-05-01), Yao
patent: 5779797 (1998-07-01), Kitano
patent: 5865321 (1999-02-01), Tomanovich

Affiliated with

Also associated with

Rating

Silicon single crystal wafer annealing method and equipment and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon single crystal wafer annealing method and equipment and , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon single crystal wafer annealing method and equipment and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-843439