Silicon semiconductor rectifier chips and manufacturing...

Details Silicon semiconductor rectifier chips and manufacturing... Silicon semiconductor rectifier chips and manufacturing...

1999-03-29

2001-02-20

Mulpuri, Savitri (Department: 2811)

Semiconductor device manufacturing: process

Making regenerative-type switching device

C438S460000

Reexamination Certificate

active

06190947

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a silicon semiconductor rectifier chip, and more specifically relates to a novel method for manufacture of a plurality of semiconductor rectifier chip to omit the use of an expansion plate.
2. Description of the Prior Art
For the production of silicon semiconductor rectifier chips, as described in U.S. Pat. No. 4,638,553, “METHOD OF MANFACTURE OF SEMICONDUCTOR DEVICE”, to Anders Nilarp as inventor and assigned to International Rectifier Corporation, shown in
FIGS. 1 and 2
, the manufacturers would often adopt the most efficient standard diffusion method, to make the rectifier diode chips. The first step in the general production method is to diffuse the two sides of silicon wafer with dopant of five-valance element (such as phosphor, arsenic, etc.) and dopant of three-valance element (such as boron, aluminum, gallium, etc.), to form a P-N junction and a n-region
24
and a p-region (expansion plate
26
with low surface resistance, at step
101
, the expansion plate
26
will be a molybdenum contact having the same diameter as a silicon semiconductor diode chip
20
and having a thickness from 30 to 120 mils, typically 60 mils. After then, the electrode surfaces of silicon wafer are plated with metal film (such as, nickel, aluminum, etc.) to form ohmic contact on the surface of the silicon wafer and enable it applicable to different types of bonding processes, such as nickel/gold plating for soft soldering, or aluminum for hard brazing, to join with conductive elements, at step
102
.
After the silicon diode wafer is prepared, the wafer is cut into small chips
20
with a certain shape and size, according to the application of the diodes, at step
103
. The open junction of the chips
20
is grinding the peripheral portions on the silicon diode chip
20
to produce round mesa shape and then is processed by chemical polish to remove the mechanical damages and coatamination caused by the separation cutting process, at step
104
. A silicon dioxide film is formed on the silicon diode chip
20
so that the chip may possess good reverse electric properties. Forming a passivation coating
28
, passivation and coating are then applied to the junction of the chip
20
, at step
105
. The final step is heat treating inherently dry the passivated the silicon diode chip
20
and the processing of the chip
20
is completed, at step
106
.
With regard to the production of the rectifier chips, there are three categories of major conventional design and processing:
I) The semiconductor wafer is cut into chips, the chips are soldered with the electrical conducting elements, to become soldered sub-assembly, followed by chemical treatment and passivation in the chip cutting surface. Such as the sandwich cell construction, the axial lead plastic molded package, developed in the early stage of the industry. This category includes the “Sandwich Cell Construction”, as developed by Westinghouse in the early days, and the “Axial Lead Plastic Molded Package” method etc.
II) The rectifier diode chips with aluminum film is cut into mesa shaped chips by sand blasting method. The chips are then subjected to low-temperature chemical etching with etched chip is than hard brazed to two electrodes, usually made of tungsten or molybdenum and copper lead wire. The lead mounted subassembly is then processed by secondary junction etching, passivation glass powder slurry coating and firing to form a bead shaped glass encapsulation over the electrodes-silicone chip portion. This approach was developed by General Electric and was patented in the United States.
III) After the wafer diffusion completed, photoresist etching agent is applied, to proceed with selective partial chemical etching, to make a etch groove from the p surface, so the P-N junction of each chip element is etched and exposed. The wafer is processed with passivation treatment and glass coating. The final manufacturing steps are metallization and chip separation cutting to obtain the glass passivated pellet, or shortened as GPP.
The GPP has better performance than sandwich cell construction, so the GPP is generally employed by all types of rectifier circuit modules, such as bridge rectifiers, small outline diode (shortened as SOD), etc. However, the configuration of open P/N junction of GPP is negative beveled, the passivation glass coating covers limited areas with constricted thickness. All these result in its reverse electrode performance not reaching the optimum levels. GPP also requires more silicone wafer area than its characteristical requirement to enable to process multi-unit in wafer form.
Furthermore, the chips made by this method will inevitably result in a quality risk of mechanical damage on the glass film during the cutting and separating process, and consequently, micro crack will occur, and the tension is concentrated. Such a circumstance, in operation, will become a quite serious operational failure source. Though the manufacturers have been trying very hard for the past decades, the efficiency of possible improvement on above defects is quite limited.
As previously discussed, one method employed to avoid that damages to the glass passivation layer during the cutting process in the GPP approach is described in U.S. Pat. No. 4,638,553 discussed above. Nevertheless, the method of Nilarp, in which the silicon semiconductor diode chip
20
are brazed layers having a thickness from 30 to 120 mils before the polishing step is carried out. The thickness of the expansion plate
26
would be required for sealing the passivation coating
28
, otherwise, the cutting surfaces of the diode chip
20
cannot be sealed with a layer of passivation glass from N-region
24
to P-region without the expansion plate
26
. The production costs are also high.
Therefore, a novel structure of silicon semiconductor diode chip and a new method to prepare the diode chip are continuously being sought to overcome the disatisfaction of the GPP approach and eliminate the expansion plate.
SUMMARY OF THE INVENTION
In accordance with the present invention, a semiconductor diode chip to omit the use of an expansion plate and its preparation method are provided wherein the electrodes may be evaported aluminum, nickel, silver or gold plated. After the wafer diffusion is completed to form the P-N junction of the semiconductor wafer, the wafer is cut into a plurality of individual wafer dices. A glass passivation layer is prepared on each single piece of semiconductor rectifier dice by a simplified fixture and is fired separately for forming a passivation coating which sealing the cutting surface of the rectifier dice before the individual semiconductor rectifier chip is metallized to form ohmic contact. Damages to the glass passivation layer during the cutting process in the GPP approach may be avoide, and the manufacture cost needed by semiconductor rectifier may be reduced because it does not require attachment to the expansion plate with 60 mils thickness.
The silicon semiconductor rectifier of this invention may has a positive beveled cut at the cutting surface; the peak reverse voltage being enhanced and the possibility of leakage reduced.
The above and other objects and advantages of this invention may be more clearly understood from the following description by referring to the drawings.


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