Silicon pillars for vertical transistors

Electrical connectors – With insulation other than conductor sheath – Plural-contact coupling part

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21532

Reexamination Certificate

active

07413480

ABSTRACT:
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

REFERENCES:
patent: 3941629 (1976-03-01), Jaffe
patent: 4139442 (1979-02-01), Bondur et al.
patent: 4333964 (1982-06-01), Ghezzo
patent: 4472459 (1984-09-01), Fisher
patent: 4508757 (1985-04-01), Fabricius et al.
patent: 4551910 (1985-11-01), Patterson
patent: 4615762 (1986-10-01), Jastrzebski et al.
patent: 4630356 (1986-12-01), Christie et al.
patent: 4746630 (1988-05-01), Hui et al.
patent: 4789560 (1988-12-01), Yen
patent: 4903344 (1990-02-01), Inoue
patent: 4959325 (1990-09-01), Lee et al.
patent: 4965221 (1990-10-01), Dennison et al.
patent: 5041898 (1991-08-01), Urabe et al.
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5087586 (1992-02-01), Chan et al.
patent: 5128274 (1992-07-01), Yabu et al.
patent: 5149669 (1992-09-01), Hosaka
patent: 5210046 (1993-05-01), Crotti
patent: 5252504 (1993-10-01), Lowrey et al.
patent: 5260229 (1993-11-01), Hodges et al.
patent: 5316966 (1994-05-01), Van Der Plas et al.
patent: 5334548 (1994-08-01), Shen et al.
patent: 5358894 (1994-10-01), Fazan et al.
patent: 5409563 (1995-04-01), Cathey
patent: 5438016 (1995-08-01), Figura et al.
patent: 5457067 (1995-10-01), Han
patent: 5458999 (1995-10-01), Szabo et al.
patent: 5466632 (1995-11-01), Lur et al.
patent: 5468675 (1995-11-01), Kaigawa
patent: 5607874 (1997-03-01), Wang et al.
patent: 5747377 (1998-05-01), Wu
patent: 5789306 (1998-08-01), Roberts et al.
patent: 5834359 (1998-11-01), Jeng et al.
patent: 5895273 (1999-04-01), Burns et al.
patent: 5899727 (1999-05-01), Hause et al.
patent: 5909630 (1999-06-01), Roberts et al.
patent: 6008106 (1999-12-01), Tu et al.
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6104068 (2000-08-01), Forbes
patent: 6150687 (2000-11-01), Noble et al.
patent: 6306727 (2001-10-01), Akram
patent: 6320222 (2001-11-01), Forbes et al.
patent: 6350635 (2002-02-01), Noble et al.
patent: 6355961 (2002-03-01), Forbes
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6377070 (2002-04-01), Forbes
patent: 6399979 (2002-06-01), Noble et al.
patent: 6413825 (2002-07-01), Forbes
patent: 6414356 (2002-07-01), Forbes et al.
patent: 6424001 (2002-07-01), Forbes et al.
patent: 6448601 (2002-09-01), Forbes et al.
patent: 6492233 (2002-12-01), Forbes et al.
patent: 6496034 (2002-12-01), Forbes et al.
patent: 6504201 (2003-01-01), Noble et al.
patent: 6531727 (2003-03-01), Forbes et al.
patent: 6559491 (2003-05-01), Forbes et al.
patent: 6566682 (2003-05-01), Forbes
patent: 6639268 (2003-10-01), Forbes et al.
patent: 6664806 (2003-12-01), Forbes et al.
patent: 6670642 (2003-12-01), Takaura et al.
patent: 6734482 (2004-05-01), Tran et al.
patent: 6734484 (2004-05-01), Wu
patent: 6756625 (2004-06-01), Brown
patent: 6797573 (2004-09-01), Brown
patent: 6798009 (2004-09-01), Forbes et al.
patent: 6801056 (2004-10-01), Forbes
patent: 6806137 (2004-10-01), Tran et al.
patent: 6808979 (2004-10-01), Lin et al.
patent: 2003/0227072 (2003-12-01), Forbes et al.
patent: 53-148389 (1978-12-01), None
patent: 60-167349 (1985-08-01), None
patent: 1-100948 (1989-04-01), None
patent: 2-219253 (1990-08-01), None
patent: 4-130630 (1992-05-01), None
patent: 4-162528 (1992-06-01), None
“Notes from IEDM, part 3,” http://www.thinfilmmfg.com/Noteworthy/Noteworthy01/IEDM12Dec01.htm, 2 pages (Dec. 12, 2001).
Lau et al., “High aspect ratio submicron silicon pillars fabricated by photoassisted electrochemical etching and oxidation,”Applied Physics Letters,vol. 67(13), pp. 1877-1879 (Sep. 25, 1995).
Lau et al., “High aspect ratio sub-micron pillars for light emission studies and photonic band gap material applications,” 1995/6 Research Journal, Microelectronics Group, 3 pages (Jun. 1996).
Lutze et al., “Field oxide thinning in poly buffer LOCOS isolation with jActive area spacings to 0.1 μm,”Journal of Electrochemical Society,vol. 137, No. 6, pp. 1867-1870 (Jun. 1990).
Seeger et al., “Fabrication of ordered arrays of silicon nanopillars,”J. Phys. D: Appl. Phys.,vol. 32, pp. L129-L132 (1999).
Wolf et al., “Silicon processing for the VLSI era,” vol. 1, Lattice Press, CA, USA, pp. 529-555 (1986).
“Quantum confinement effects in a 3D FinFET transistor,” http://www.ise.com/appex/FinFET/FinFET.html, 5 pages (Jan. 15, 2003).
Clarke, Peter, “ISSCC: Vertical transistor structures considered,”EE Times Website,http://www.eetimes.com, 3 pages (Feb. 9, 2000).
Goebel et al., “Fully depleted surrounding gate transistor (SGT) for 70 nm DRAM and beyond,”IEEE,5 pages (2002).
Mandelman et al., “Challenges and future directions for the scaling of dynamic random-acess memory (DRAM),”IBM J. RES.&DEV.,vol. 46, No. 2/3, pp. 187-212 (Mar./May 2002).
P. Xuan et al., “60nm planarized ultra-thin body solid phase epitaxy MOSFETs,” IEEE Device Research Conf., Denver, CO, pp. 67-68, Jun. 2000.
P. Kalavade et al., “A novel sub-10nm transistor,” IEEE Device Research Conf., Denver, CO pp. 71-72, Jun. 2000.
J.P. Denton et al., “Fully depleted dual-gate thin-film SOI p-MOSFET's fabricated in SOI islands with an isolated buried polysilicon backgate,”IEEE Electron Device Lett.,vol. 17, No. 11, pp. 509-511, Nov. 1996.
Xuejue Huang, et al., “Sub-50 nm P-Channel FinFET,”IEEE Transactions on Electron Devices,vol. 48, No. 5, May 2001.
J. Kedzierski, et al., “High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices”IEDM,2001, paper 19.5.
K. Kim, et al., “Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device” International Symposium on Low Power Electronics and Design Newport Beach Marriott Hotel, Newport, California, Aug. 9-11, 2004, http://www.islped.org.
B.S. Doyle, et al., “High performance fully-depleted tri-gate CMOS transistors,”IEEE Electron Device Letters,vol. 24, No. 4, Apr. 2003, pp. 263-265.
B. Doyle, et al., “Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout,” 2003Symposium on VLSI Technology.Digest of Technical Papers, Tokyo; Japan Soc. Applied Phys, 2003, pp. 133-134.
H. Takato, et al. “High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs”IEEE Electron Devices Meeting,Technical Digest, pp. 222-225, 1998.
S. Miyano, et al., “Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA),”IEEE Transactions on Electron Devices,vol. 39, No. 8, Aug. 1992, pp. 1876-1881.
H-S P. Wong et al., “Self-aligned (top and Bottom) Double-Gate MOSFET with a 25nm Thick Silicon Channel,”IEEE Int. Electron Device Meeting,1997, pp. 427-430.
Hyun-Jin Cho, et al., “A novel pillar DRAM cell 4 Gbit and beyond,”Digest of Technical Papers Symposium on VLSI Technology,Jun. 9-11, 1998, pp. 38-39.
W. Sakamoto, et al., “A study of current drivability of SGT,”Record of Electrical and Communication EngineeringConversazione Tohuku University, vol. 72, No. 2, Feb. 2004, pp. 110-111.
R. Nishi, et al., “Concave Source SGT for suppressing punch-through effect,”Transactions of the Institute of Electronics, Information and Communication EngineersC, vol. J86-C, No. 2, Feb. 2003, pp. 200-201.
W. Zhang, et al., :A study of load capacitance in SGT,Record of Electrical and Communication EngineeringConversazione Tohuku University, vol. 71, No. 1, Oct. 2002, pp. 473-474.
H. Yamashita, et al., “A study of process design in three dimensional SGT device,”Record of Electrical and Communication EngineeringConversazione Tohoku University, vol. 71, No. 1, Oct. 2002, pp. 467-468.
C.K. Date, et al., “Suppression of the floating-body

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Silicon pillars for vertical transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon pillars for vertical transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon pillars for vertical transistors will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3993903

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.