Silicon oxycarbide and silicon carbonitride based materials...

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

Reexamination Certificate

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C257S325000, C257S411000, C257S632000, C257S639000, C257S760000

Reexamination Certificate

active

07115974

ABSTRACT:
In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.

REFERENCES:
patent: 6127262 (2000-10-01), Huang et al.
patent: 6209484 (2001-04-01), Huang et al.
patent: 6277764 (2001-08-01), Shin et al.
patent: 6861686 (2005-03-01), Lee et al.
patent: 2004/0124420 (2004-07-01), Lin et al.
Maszara, W.P., et al., “SOI and Strain: CMOS Performance Enhancers,” Solid State Technology, WaferNEWS, http://sst.pennnet.com/Articles/Article—Display.cfm?Section=ARTCL&ARTICLE—ID=182802&VERSION—NUM=1&p=5.
Rim, K., “Strained Silicon and SOI: Complementary Technologies,” Solid State Technology, WaferNEWS, http://sst.pennnet.com/Articles/Article—Display.cfm?Section=ARTCL&ARTICLE—ID=182802&VERSION—NUM=1&p=5.

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