Silicon-on-insulator wafer for RF integrated circuit

Details Silicon-on-insulator wafer for RF integrated circuit Silicon-on-insulator wafer for RF integrated circuit

2002-07-01

2004-06-01

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S406000, C438S455000, C438S458000, C438S459000, C148SDIG001, C257S593000, C257S676000, C257S701000

Reexamination Certificate

active

06743662

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to silicon-on-insulator (SOI) wafers for RF integrated circuits.
BACKGROUND OF THE INVENTION
The material requirements for the initial processing of the silicon used in a particular application are driven by that application. For RF applications, these material requirements are very stringent. Standard bulk silicon wafers or silicon-on-insulator wafers use low resistivity substrates that result in high losses and cross-talk at high frequencies. For example, the Q's of inductors fabricated using silicon wafers or silicon-on-insulator wafers having low resistivity substrates are low. Therefore, multi-level metals with a ground plane are used in order to achieve higher Q's. However, these coupling techniques result in cross-talk. In addition, losses increase at higher frequencies due to the low resistivity of the substrates.
Losses and coupling (cross-talk) in RF applications may be reduced by using high resistivity silicon (HRS) substrates. Such substrates have maximum resistivities &rgr; of 10
4
&OHgr;-cm as compared to a resistivity &rgr; of about 10 &OHgr;-cm for the silicon substrate typically used. However, the resistivity of HRS is 3-4 orders of magnitude lower than a GaAs substrate commonly used for RF applications. In addition, there is a problem with using high resistivity silicon substrates in RF applications. That is, during post-processing, thermally generated donors degrade the resistivity both at the SiO
2
/Si interface and at the back of the wafer, as shown by the graphs in
FIGS. 1 and 2
.
FIG. 1
is a resistance profile at the interface between the buried oxide and the substrate (i.e., the SiO
2
/Si interface) where the substrate is assumed to be an n-type substrate. The y-axis of
FIG. 1
represents resistivity, and the x-axis represents depth into the substrate. The point at which x=0 is at the interface. As shown in
FIG. 1
, the resistivity of the substrate is lowest just below the interface.
FIG. 2
is a resistance profile across a p-type wafer. The y-axis of
FIG. 2
represents resistivity, and the x-axis represents depth into the wafer. The point at which x=0 is at the front surface of the wafer. As shown in
FIG. 2
, the back of the wafer, under certain conditions, may actually undergo a conversion in type (in this case, from p type to n type). It has also been observed that, under other conditions, the region of the wafer just below the buried oxide may also undergo a conversion in type.
The degradation at the back of the wafer may be removed by grinding. However, the degradation at the interface produces higher losses, increases coupling (cross-talk), lowers inductor Q, and is not so easily remedied. The present invention solves one or more of these problems
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, an RF semiconductor device comprises a high resistivity polysilicon handle wafer, a buried oxide layer over the polysilicon handle wafer, and a silicon layer over the buried oxide layer.
In accordance with another aspect of the present invention, an RF semiconductor device comprises a high resistivity polycrystalline layer, a buried oxide layer over the polycrystalline layer, and a silicon layer over the buried oxide layer.
In accordance with still another aspect of the present invention, a method of fabricating an RF semiconductor device comprises the following: forming an oxide layer on a surface of a first wafer, wherein the first wafer comprises low resistivity silicon; and, bonding the oxide layer of the first wafer to a second wafer, wherein the second wafer comprises a high resistivity polysilicon wafer, whereby the RF semiconductor device is produced.
In accordance with yet another aspect of the present invention, a method of fabricating an RF semiconductor device comprises the following: forming a first oxide layer on a surface of a first wafer, wherein the first wafer comprises a high resistivity polycrystalline material; forming a second oxide layer on a surface of a second wafer, wherein the second wafer comprises low resistivity silicon; and, bonding the first and second oxide layers against one another so as to produce the RF semiconductor device.
In accordance with a further aspect of the present invention, a method is provided to fabricate an RF semiconductor device starting with a SOI wafer having a top silicon layer, a buried oxide layer, and a bottom silicon layer. The method comprises the following: forming a new oxide layer on a surface of the top silicon layer; forming a high resistivity polysilicon layer over the new oxide layer; removing the bottom silicon layer of the SOI wafer; and, removing the buried oxide layer of the SOI wafer so as to produce the RF semiconductor device.


REFERENCES:
patent: 5168078 (1992-12-01), Reisman et al.
patent: 5266135 (1993-11-01), Short et al.
patent: 5362667 (1994-11-01), Linn et al.
patent: 5387555 (1995-02-01), Linn et al.
patent: 5569620 (1996-10-01), Linn et al.
patent: 5728624 (1998-03-01), Linn et al.
patent: 5773355 (1998-06-01), Inoue et al.
patent: 5801084 (1998-09-01), Beasom et al.
patent: 5849627 (1998-12-01), Linn et al.
patent: 6150197 (2000-11-01), Boles et al.
patent: 6183857 (2001-02-01), Litwin et al.
patent: 6239004 (2001-05-01), Aga et al.
patent: 6251751 (2001-06-01), Chu et al.
patent: 6255731 (2001-07-01), Ohmi et al.
patent: 6265248 (2001-07-01), Darmawan et al.
patent: 6291324 (2001-09-01), Lescot et al.
patent: 6352909 (2002-03-01), Usenko
patent: 6388290 (2002-05-01), Celler et al.
patent: 6410371 (2002-06-01), Yu et al.
patent: 6465324 (2002-10-01), Vogt et al.
patent: 2002/0008268 (2002-01-01), Babcock et al.
patent: 2002/0092307 (2002-07-01), Ghoshal
I. Lagnado et al., RF System Based on Silicon-on-Saphire Technology, Oct. 200, IEEE, 2000 IEEE International Conference, Oct. 2000, pp. 32-33.*
James G. Fiorenza et al., RF Power LDMOSFET on SOI, Mar. 2001, IEEE, vol. 22 No. 3, IEEE Electron Device LEtters, pp. 139-141.*
Satoshi Matsumoto et al. A High-Efficiency Thin-Film SOI Power MOSFET Having a Self-Aligned Offset Gate structure for Multi_Gegahertz Applications. Jun. 2001, IEEE, IEEE Transactions on Electron devices, vol. 48, No. 6, Jun. 2001 pp. 1270-1274.*
Y. Hiraoka et al., New Substrate-crosstalk reduction structure using SOI substrate, Oct. 2001, IEEE International SOI Conference, p. 107-108.*
V. Cuocs et al., A Novel vertical DMOS Transistor in SOA Technology for RF-power Applications, May 2002, Proc. 23rd. International Conference On MicroElectronics(MIEL 2002), vol. 1 NIS, Yugoslaia, May 12-15, 2002 pp. 159-161.*
Alberto O. Adan et al., LInerarity and Low-Noise Performance of SOI MOSFETs for RF Applications., May 2002, IEEE TRansactions on Electron Devices, vol. 49, No. 5, May 2002, pp. 881-888.*
Peter Van Zant, MIcrochip Fabrication, A practical Guide to Semiconductor Processing, Fourth Edition, McGraw-Hill, pp. 32-34.*
Satoshi Matsumoto et al., A Novel High_Speed Quasi-SOI Power MOSFET with Supressed Parasitic Bipolar Effect Fabricated by reversed Siulicon Wafer Direct Bonding,96- 1996, IEDM, pp. 18.81 to 18.8.03.*
Digh Hisamoto et al., Silicon RF Devices Fabricated by ULSI Processes Featuring ).1 Um SOI_CMOS and Suspended Inductors, 1996, Symposium on VLSI Technology Digest Of Techinical Papers , IEEE, pp. 104-105.*
Satoshi Matsumoto et al., Study on the Device Characterisitcs of a Quasi-SOI Power MOSFET Fabricated by reversed Silicon wafer Direct Bonding, Sep. 1998, vol. 45, No. 9, IEEE, pp. 1940-1945.*
A.O.Adan et al., SOI as a Mainstream IC Technology, Oct. 1998, Proceedings 1998 IEEEInterantional SOI Conference pp. 9-12.

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