Silicon-on-insulator substrates using low dose implantation

Details Silicon-on-insulator substrates using low dose implantation Silicon-on-insulator substrates using low dose implantation

1999-05-14

2001-03-20

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S347000

Reexamination Certificate

active

06204546

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor substrates or wafers and more particularly, to silicon-on-insulator substrates using separation by implantation of oxygen (SIMOX) to provide a layer of single crystal silicon on a silicon dioxide layer over a substrate of silicon.
BACKGROUND OF THE INVENTION
Silicon-On-Insulator (SOI) substrates may be fabricated by a process known as separation by implantation of oxygen (SIMOX). A large part of the cost to fabricate SOI substrates is the time required to implant oxygen by an ion implanter. Quality, thickness and uniformity of the top silicon layer, quality, thickness and uniformity of the buried oxide layer, silicon defect thickness above the buried oxide layer are variables in the SOI substrates resulting from the particular SIMOX fabrication process used.
There is an increasing interest in low-dose (LD) SIMOX to reduce the time of implantation and thus the cost of SOI substrates. The lower dose results in less machine time required to implant the oxygen. Furthermore, the structural and electrical quality of the Si active layer improves in the LD SIMOX material. The standard procedures used for LD SIMOX typically have the following deficiencies: (1) a buried oxide (BOX) breakdown voltage V
bd
Of less than 8 MV/cm, (2) electrical shorts such as 5 to 10 shorts cm
−2
, (3) Si islands within the BOX of 10
3
to 10
4
islands cm
−2
, and (4) a rough Si surface.
SUMMARY OF THE INVENTION
In accordance with the present invention, an SOI substrate and method for forming SOI substrates is described comprising the steps of heating a major surface of a silicon substrate in the range from about 515° C. to about 635° C. and preferably about 590° C., first implanting ions of O
+
at an energy in the range from about 70 keV to about 200 keV and preferably about 170 keV into the major surface of the silicon substrate with a dose in the range from about 1.0×10
17
cm
−2
to about 3.5×10
17
cm
−2
and preferably about 3×10
17
cm
−2
, cooling the major surface of the silicon substrate below 300° C. such as about 23° C., second implanting ions of O
+
at an energy in the range from about 70 keV to about 200 keV and preferably about 170 keV into the major surface of the silicon substrate with a dose in the range from about 7×10
14
cm
−2
to about 2×10
15
cm
−2
and preferably about 9×10
14
cm
−2
, first annealing the major surface of the silicon substrate at a temperature in the range from about 1250° C. to about 1400° C. and preferably about 1320° C. for about 6 hrs in an ambient containing O
2
such as 0.2 to 2% O
2
, stripping the surface oxide and second annealing the major surface of the silicon substrate at a temperature in the range from about 1300° C. to about 1400° C. for about 1 to 4 hrs. and preferably about 1350° C. for about 2 hrs 40 min in an ambient containing O
2
such as 50% O
2
.
The invention provides a high quality buried oxide layer with extremely low doses of oxygen.
The invention further provides a two step implantation of oxygen in silicon at two substrate temperatures and two respective doses followed by a two step annealing procedure at high temperatures at two respective oxygen ambients.
The invention further provides a two step high temperature oxidation anneal to eliminate defects in the silicon above the buried oxide by forming silicon dioxide as part of the buried oxide in the region where the defects were present.
The invention further provides a buried oxide layer of uniform thickness with a smooth continuous buried oxide upper surface.
The invention further provides a buried oxide layer with a breakdown voltage greater than 8 MV/cm and with shorts less than 1 short/cm
2
.


REFERENCES:
patent: 5891265 (1999-04-01), Nakai et al.
patent: 6043166 (2000-03-01), Roitman et al.

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