Silicon-on-insulator (SOI) transistor having partial hetero...

Details Silicon-on-insulator (SOI) transistor having partial hetero... Silicon-on-insulator (SOI) transistor having partial hetero...

2002-05-15

2004-03-16

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S311000

Reexamination Certificate

active

06706614

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to silicon-on-insulator (SOI) devices and methods of forming the same and, more particularly, to SOI devices and methods for forming which avoid or reduce floating body effects.
BACKGROUND ART
Silicon-on-insulator (SOI) materials offer potential advantages over bulk materials for the fabrication of high performance integrated circuits. Dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and packing density greatly increased if the devices are made without body contacts (i.e., if the body regions of these devices are “floating”). However, partially-depleted metal oxide semiconductor field effect transistors (MOSFETs) on SOI materials typically exhibit parasitic effects due to the presence of the floating body (“floating body effects”). These floating body effects may result in undesirable performance in SOI devices.
It will be appreciated from the foregoing that a need exists for SOI MOSFETs having reduced floating body effects.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a silicon-on-insulator (SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hetero junction along a lower portion of the source/body junction.
According to another aspect of the invention, the invention is a method of fabricating a silicon-on-insulator (SOI) transistor. The method including the steps of providing an active layer disposed on a buried oxide (BOX) layer, the BOX layer being disposed on a substrate, the active layer having an active region defined by isolation regions; forming a transistor in the active region, the transistor having a source and a drain having a body disposed therebetween, and a gate disposed on the body, and implanting the source with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hetero junction along a lower portion of the source/body junction.


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