Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-04-11
2004-05-18
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C210S211000
Reexamination Certificate
active
06737900
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electrical divide-by circuits for dividing down signals, and more particularly to dynamic d-type flip-flop circuits used in digital devices such as microprocessors, digital signal processors, prescalers and digital counters.
2. Description of Related Art
Digital devices frequently utilize circuits that are capable of storing data (i.e., “memory” circuits). One exemplary basic memory circuit is the well-known d-type flip-flop (DFF). Exemplary digital devices that utilize DFFs include microprocessors, digital signal processors, prescalers, and digital counters.
One objective of DFF design is to increase the maximum operating frequency of the DFF circuits. The “maximum operating frequency” (MOF) is defined as the highest clock frequency at which a DFF maintains stable operation (ie., maintains accurate data storage). Several exemplary “dynamic” DFF circuits are now described. The term dynamic refers to the well-known, low-power, high-speed technique of temporarily storing digital information (e.g., a data bit) in the nodal capacitance at the gate of a MOS transistor. This capacitance can include both the parasitic and gate capacitance.
A first exemplary DFF circuit is referred to as a true single phase clock d-type flip-flip (TSPC DFF) circuit and is described in more detail in an article by Yuan and Svensson, entitled “High-Speed CMOS Circuit Technique” published in the IEEE Journal of Solid State Circuits, 24(1), pages 62-70 in 1989 by IEEE, which is hereby incorporated by reference herein for its teachings on digital circuits design. The TSPC DFF is widely implemented as a high-speed DFF in speed-critical applications.
FIG. 1
is a schematic diagram of an exemplary TSPC DFF circuit. As shown in
FIG. 1
, the exemplary TSPC DFF circuit
100
includes nine transistors: N
1
14
, N
2
16
, N
3
26
, N
4
36
, P
1
12
, P
2
22
, P
3
24
, P
4
32
and P
5
34
. For simplification, the description of the inventive uses the following nomenclature: transistors with an “N” prefix (e.g., N
3
26
) comprise NMOS transistors. Transistors with a “P” prefix (e.g., P
5
34
) comprise PMOS transistors. Those skilled in the electrical circuit design arts shall recognize that alternative terms can be used without departing from the scope or spirit of the present invention. A clock signal inputs to 4 transistors: N
1
14
, P
2
22
, N
3
26
and P
5
34
.
The exemplary TSPC DFF circuit
100
typically comprises three stages. Each stage typically comprises a set of “stacked” transistors, wherein elements are vertically “stacked”. For example, a first stage comprises transistors P
1
12
, N
1
14
and N
2
16
; a second stage comprises transistors P
2
22
, P
3
24
and N
3
26
; and a third stage comprises transistors P
4
32
, P
5
34
and N
4
36
. In the exemplary TSPC DFF circuit
100
the relative sizes of transistors within each stage are not critical to the proper operation of the circuit. The exemplary TSPC DFF circuit
100
is described in greater detail in the above-incorporated article by Yuan and Svensson, and thus is not described in more detail herein. A stand exemplary DFF circuit is now described with reference to FIG.
2
.
A second exemplary DFF circuit improves upon the first exemplary DFF circuit by implementing well-known “ratioed logic” techniques. To function properly, ratioed logic techniques require that the PMOS and NMOS transistors within a stage have a specific transistor size (ie., dimension or width/length (W/L)) ratio. Ratioed logic techniques are well known, and thus are not described in more detail herein. Exemplary ratioed logic techniques are described in a book by Van Valkenburg, entitled “Reference Data for Engineers, eighth edition” published in 1995 by Sams publishing, chapter 20, pages 20-35 and 20-36, which is hereby incorporated by reference herein for its teachings on ratioed logic circuit design techniques. Using ratioed logic techniques advantageously reduces the number of transistors needed in circuit implementations, and thus, increases circuit speed.
The second exemplary DFF circuit comprises only 7 transistors, whereas the first exemplary TSPC DFF circuit
100
comprises 9 transistors. The second exemplary circuit is referred to as a “New Dynamic D-Type Flip-Flop” (ND DFF) and is described in detail in an article by Chang et al., entitled “A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,” published in the IEEE Journal of Solid State Circuits, 31(5), at pages 749-752 in 1996 by IEEE. The article is hereby incorporated by reference herein for its teachings on digital circuit design.
FIG. 2
is a schematic diagram of an exemplary ND DFF. As shown in
FIG. 2
, the exemplary ND DFF circuit
200
comprises 7 transistors: N
1
14
, N
2
16
, N
3
26
, N
4
36
, P
1
12
, P
2
22
and P
5
34
. A clock signal is input into
3
transistors: N
1
14
, N
3
26
and P
5
34
. The exemplary ND DFF
200
advantageously exhibits less clock loading than does the TSPC DFF described above with reference to FIG.
1
. Specifically, the clock driver of the TSPC DFF
100
of
FIG. 1
drives four transistors (specifically, the transistors N
1
14
, P
2
22
, N
3
26
and P
5
34
), whereas the clock driver of the exemplary ND DFF
200
of
FIG. 2
drives only three transistors (N
1
14
, N
3
26
and P
5
34
).
The ND DFF circuit
200
typically includes three transistor stages. A first stage comprises the transistors P
1
12
, N
1
14
and N
2
16
; a second stage comprises the transistors P
2
22
and N
3
26
; and a third stage comprises the transistors P
5
34
and N
4
36
. The second stage of the exemplary ND DFF circuit
200
uses a ratioed logic technique. The ratioed logic technique requires a transistor size ratio between P
2
and N
3
to be selected so that when P
2
and N
3
are both “on”, (i.e., conducting) node B is below the V
IL
of N
4
. Similarly, the third stage also implements ratioed logic where the QB
6
is below the V
IL
of an output buffer (not shown in
FIG. 2
) connected to the QB
6
. The exemplary ND DFF
200
is described in greater detail in the above-incorporated article by Chang et al., and thus is not described in more detail herein. A third exemplary DFF circuit is now described with reference to FIG.
3
.
A third exemplary DFF circuit improves upon the second exemplary DFF circuit by using fewer transistors, and thereby improves circuit performance. The third exemplary DFF circuit includes only 6 transistors, whereas the second exemplary DFF circuit
200
includes 7 transistors. The third exemplary circuit is referred to as an “Extended True-Single-Phase-Clock D-Type Flip-Flop” (E-TSPC DFF).
FIG. 3
is a schematic diagram of an exemplary E-TSPC DFF. As shown in
FIG. 3
, the exemplary E-TSPC DFF circuit
300
includes 6 transistors: N
1
14
, N
3
26
, N
4
36
, P
1
12
, P
2
22
and P
5
34
. A clock signal (referred to hereinafter as either “CLK” or “C”)
4
,
4
′, and
4
″ inputs respectively to 3 transistors: N
1
14
, N
3
26
and P
5
34
. The exemplary E-TSPC circuit
300
includes three transistor stages. As shown in
FIG. 3
, a first stage
51
includes the stacked transistors P
1
12
and N
1
14
; a second stage
52
includes the stacked transistors P
2
22
and N
3
26
; and a third stage
53
includes the stacked transistors P
5
34
and N
4
36
. The third exemplary DFF circuit
300
is substantially similar to the second exemplary DFF circuit
200
(FIG.
2
), and thus is not described in more detail herein. Identical components function similarly in both circuits.
One embodiment of the third exemplary DFF circuit
300
is referred to as a “Ratioed Logic Extended True-Single-Phase-Clock D-type Flip-Flop” (RL E-TSPC DFF) and is described in an article by Soares and Van Noije, entitled “A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC),” published in 1999 in the IEEE Journal of Solid State Circuits, 34(1), at pages 97-102 (and at FIG.
6
), by IEEE. The article is hereby incorporated by reference herein for i
Boling, Esq. William C.
Jaquez & Associates
Jaquez, Esq. Martin J.
Lam Tuan T.
Peregrine Semiconductor Corporation
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