Silicon-on-insulator diodes and ESD protection circuits

Details Silicon-on-insulator diodes and ESD protection circuits Silicon-on-insulator diodes and ESD protection circuits

2002-12-10

2003-11-25

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Avalanche diode

C257S212000, C257S347000, C257S349000, C257S350000, C257S551000, C257S603000, C438S311000

Reexamination Certificate

active

06653670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to diodes in silicon-on-insulator (SOI) CMOS process, and more particularly to ESD protection circuits with the diodes in silicon-on-insulator CMOS process.
2. Description of the Prior Art
Silicon-on-insulator technology is a prime contender for low voltage, high speed applications because of its advantages over bulk-Si technology in reduced process complexity, latch-up immunity and smaller junction capacitance. However, electrostatic discharge (ESD) is a major reliability concern for SOI technology.
The protection level provided by an ESD protection device is determined by the amount of current that it can sink. The device failure is initiated by thermal runaway and followed by catastrophic damage during an ESD pulse. In SOI devices, the presence of the buried oxide layer having a thermal conductivity {fraction (1/100)}
th
of Si causes increased device's heating, which in turn accelerates thermal runaway.
FIG. 1
depicts a cross-sectional view of a prior SOI diode, called as Lubistor diode, published in the article of the Proc. Of EOS/ESD Symp., 1996, pp. 291-301. If the silicon layer above the buried oxide layer
100
is doped N type dopant, the junction of the SOI diode is P+
102
/N well
101
. The two terminals of this junction diode are V
1
connected to P+
102
and V
2
connected to N well
101
. If V
1
is positive relative to V
2
, the SOI diode is under forward biased. However, if V
1
is negative relative to V
2
, the diode is under reverse biased. If the P+
102
/N well
101
(or N+/P well) junction area in which the power is generated during an ESD event is smaller, then it will increase power density and heat. The heat is generated in a localized region at the P-N junction and the dominant component of the heat at the junction is Joule heat. Second breakdown is assumed to occur when the maximum temperature in the SOI diode reaches the intrinsic temperature (T
intrinsic
). In order to get better ESD protection level, one should reduce the power density and Joule heat.
Accordingly, it is a desirability to provide a diode with lower power density in silicon-on-insulator CMOS process for ESD protection.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a silicon-on-insulator diode with more junction area than a normal one, thereby a lower power density and heating are obtained, and the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) is improved.
It is another object of the present invention to provide a silicon-on-insulator diode with more junction area than a normal one, which could be used in the I/O ESD protection circuit and the Vdd-to-Vss ESD protection circuit under forward biased condition.
It is a further object of the present invention to provide an I/O ESD protection circuit having SOI diodes with more junction area than normal ones, which can reduce the parasitic input capacitance, and could serve as the I/O ESD protection circuit in the RF circuits or HF circuits.
In order to achieve the above objects, the present invention provides a silicon-on-insulator diode and ESD protection circuit thereof. The silicon-on-insulator diode comprises a substrate, an insulating layer, two shallow trench isolations, and a PN junction diode formed of a first well with a first conductive type having either of N type and P type and a second well with a second conductive type opposite to the first conductive type. The insulating layer is formed on the substrate and then the two shallow trench isolations are formed thereon. The PN junction diode is formed between the two shallow trench isolations. While, the ESD protection circuit having the SOI diodes comprises an electrically conductive pad, a conductor segment, a first voltage supply rail, a second voltage supply rail, a first diode, a second diode, a first plurality of diodes and a second plurality of diodes. All of which are fabricated on the insulating layer. The conductor segment connects the pad directly to a first node. The first diode connects between the first node and the first voltage supply rail, and the second diode connects between the first diode and the second voltage supply rail. The first plurality of diodes connect between the first node and the first voltage supply rail, and which are opposite to the first diode's direction. The second plurality of diodes connect between the first node and the second voltage supply rail, and which are opposite to the second diode's direction.


REFERENCES:
patent: 5923067 (1999-07-01), Voldman
patent: 6015992 (2000-01-01), Chatterjee et al.
patent: 6531741 (2003-03-01), Hargrove et al.

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