Silicon on insulator device and layout method of the same

Details Silicon on insulator device and layout method of the same Silicon on insulator device and layout method of the same

2007-01-09

2007-01-09

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having semi-insulating component

C438S014000, C438S237000, C438S527000, C257SE27112, C257SE21545, C257SE27062, C257SE21191

Reexamination Certificate

active

10956094

ABSTRACT:
A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.

REFERENCES:
patent: 4149176 (1979-04-01), Satou et al.
patent: 4889829 (1989-12-01), Kawai
patent: 4965872 (1990-10-01), Vasudev
patent: 5650651 (1997-07-01), Bui
patent: 5744838 (1998-04-01), Matsuo et al.
patent: 5852317 (1998-12-01), Berman
patent: 6084270 (2000-07-01), Yamada
patent: 6150261 (2000-11-01), Hsu et al.
patent: 6188122 (2001-02-01), Davari et al.
patent: 6191020 (2001-02-01), Liu et al.
patent: 6215155 (2001-04-01), Wollesen
patent: 6255695 (2001-07-01), Kubota et al.
patent: 6292927 (2001-09-01), Gopisetty et al.
patent: 6303414 (2001-10-01), Ang et al.
patent: 6313508 (2001-11-01), Kobayashi
patent: 6392277 (2002-05-01), Mitani et al.
patent: 6393603 (2002-05-01), Noguchi
patent: 6421816 (2002-07-01), Ishikura
patent: 6432726 (2002-08-01), Iranmanesh
patent: 6437455 (2002-08-01), Mori et al.
patent: 6441456 (2002-08-01), Konishi et al.
patent: 6452249 (2002-09-01), Maeda et al.
patent: 6475838 (2002-11-01), Bryant et al.
patent: 6498372 (2002-12-01), Brown et al.
patent: 6649959 (2003-11-01), Hsu et al.
patent: 6979868 (2005-12-01), Chen et al.
patent: 2003/0057476 (2003-03-01), Morita et al.
patent: 2003/0062573 (2003-04-01), Murakami
patent: 0622850 (1994-02-01), None
patent: 04-280456 (1992-10-01), None
patent: 06-204467 (1994-07-01), None
patent: A 7-106579 (1995-04-01), None
patent: 10-335666 (1998-12-01), None
patent: 11-186394 (1999-07-01), None
patent: 11-204767 (1999-07-01), None
Statement of Relevance for JP A 7-106579, no date.

Affiliated with

Also associated with

Rating

Silicon on insulator device and layout method of the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon on insulator device and layout method of the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon on insulator device and layout method of the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3779667