Silicon nitride S/D ion implant mask in CMOS device fabrication

Details Silicon nitride S/D ion implant mask in CMOS device fabrication Silicon nitride S/D ion implant mask in CMOS device fabrication

1981-04-27

1983-05-10

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148187, 357 42, 357 97, H01L 21265, H01L 754

Patent

active

043828272

ABSTRACT:
A coplanar CMOS process for fabricating self-aligned gate FETs utilizing high energy, high dose rate ion implants to form the S/D regions. In the course of coplanar processing, the gate electrodes and S/D regions are defined. Selectively prescribed thicknesses of silicon dioxide are then formed over the top and sidewalls of the gate electrodes, as well as the exposed substrate in the S/D regions. Thereafter, a first, silicon nitride layer of controlled thickness is evenly deposited, and is followed by a dry etch step to expose the thin layer of silicon dioxide covering the p-channel FET S/D regions. The temperature stability of silicon nitride protects the n-channel FETs from the effects of the high energy levels and currents associated with the ion implant step used to form the S/D regions of the p-channel FETs. In contrast, the implant ions readily penetrate the thin oxides over the S/D regions of the p-channel FETs. Thereafter, a second, silicon nitride layer of controlled thickness is deposited. Again, it is followed by a dry etch step, but now to expose the silicon dioxide covering the n-channel FET S/D regions. The succeeding n-channel S/D implant similarly penetrates the silicon dioxide coverings, while the silicon nitride serves as a barrier for the remaining substrate surface. After S/D implanting is completed, a highly preferential etchant is used to remove the remaining silicon nitride, while the areas protected by the relatively thin layers of silicon dioxide are substantially unaffected.

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