Silicon interposer testing for three dimensional chip stack

Details Silicon interposer testing for three dimensional chip stack Silicon interposer testing for three dimensional chip stack

2011-01-04

2011-01-04

Picardat, Kevin M (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S015000, C438S125000, C257S685000, C257S723000

Reexamination Certificate

active

07863106

ABSTRACT:
A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer. The method thus provides same-sided probe testing of the interposer. The method also provides for loading or power application to the conductive glass handler and testing of circuits and interconnects on the test side of the silicon interposer.

REFERENCES:
patent: 4724383 (1988-02-01), Hart
patent: 5198756 (1993-03-01), Jenkins
patent: 5490028 (1996-02-01), Ang
patent: 5544774 (1996-08-01), Gray
patent: 5563754 (1996-10-01), Gray
patent: 5621594 (1997-04-01), Gray
patent: 5673474 (1997-10-01), Watterston
patent: 5684660 (1997-11-01), Gray
patent: 5737825 (1998-04-01), Gray
patent: 5748417 (1998-05-01), Malhotra
patent: 5754377 (1998-05-01), Gray
patent: 5777824 (1998-07-01), Gray
patent: 5801909 (1998-09-01), Gray
patent: 5818246 (1998-10-01), Zhong
patent: 5844412 (1998-12-01), Norton
patent: 6294908 (2001-09-01), Belmove
patent: 6521841 (2003-02-01), Kawaguchi
patent: 6528343 (2003-03-01), Kikuchi et al.
patent: 6569711 (2003-05-01), Susko et al.
patent: 6620652 (2003-09-01), Shibata
patent: 6734681 (2004-05-01), Sabey
patent: 6800537 (2004-10-01), Haba
patent: 6802930 (2004-10-01), Chuang et al.
patent: 6806581 (2004-10-01), Hsieh
patent: 6900648 (2005-05-01), Ou
patent: 7129732 (2006-10-01), Knadle
patent: 7262610 (2007-08-01), Ohtaki
patent: 7282794 (2007-10-01), Akram
patent: 7390700 (2008-06-01), Gerber
patent: 2008/0272794 (2008-11-01), Grube et al.
patent: 0 751 566 (1997-02-01), None
Bulkeley—“IBM Touts Break-Through in 3-D Chips”—The Wall Street Journal (Apr. 2007).
Dang—“3D Chip Stacking with C4 Technology”—IBM (Nov. 2008).
Jayantha—“Thermomechanical Modeling of 3d Electronic Packages”—IBM (Nov. 2008).
Knickerbocker-1—“Three-Dimensional Silicon Integration”—IBM JRD (Nov. 2008).
Knickerbocker-2—“Development of Next-Generation System-On-Package (SOP) Technology Based on Silicon Carriers with Fine-Pitch Chip Interconnection”—IBM JRD (Jul. 2005).
Manzer—“High-Speed Electrical Testing of Multichip Ceramic Modules”—IBM JRD (Sep. 2005).
Micronews—“Silicon Interposers Wait for an Application”—Web Content—I-Micronews (Jul. 2008).
Sakuma—“3D Chip-Stacking Technology with Through-Silicon Vias and Low-Volume Lead-Free Interconnections”—IBM JRD (Nov. 2008).
Lewis—“Advanced Packaging”—Jun. 2003.
Tanaka—“SiP Manufacturing Will Benefit from Caulked Connections . . . ” Renseas Tech (Copyright 2005).
Uno—“New Techniques For Module Packaging”, Tech-On (Feb. 2008).
Woods—“Jet Dispensing—The Underfill Solution”, SMT (Jan. 2005).
Das—“A High Performance C4 Probe”, 2001 Southwest Test Workshop (Jun. 4, 2001).

Affiliated with

Also associated with

Rating

Silicon interposer testing for three dimensional chip stack does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon interposer testing for three dimensional chip stack, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon interposer testing for three dimensional chip stack will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2730863