Silicon gate MOS ROM

Details Silicon gate MOS ROM Silicon gate MOS ROM

1977-10-11

1980-06-10

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

29571, 29580, 29578, 357 23, 357 45, 357 59, 365104, H01L 2704

Patent

active

042075858

ABSTRACT:
An N-channel silicon gate MOS read only memory or ROM formed by a process compatible with standard N-channel manufacturing methods but which allows the elimination of contacts between overlying metal or polysilicon lines and the semiconductor surface. Address lines are polysilicon, and output and ground lines are defined by N+ regions buried beneath field oxide. In the array, for each potential MOS transistor, a logic "1" or "0" is programmed by providing a thin oxide gate region beneath a polysilicon address line for one and providing thick field oxide for the other.

REFERENCES:
patent: 3676921 (1972-07-01), Kooi
patent: 3711753 (1973-01-01), Brand et al.
patent: 3914855 (1975-10-01), Cheney et al.
Antipov, IBM Tech. Discl. Bull., vol. 17, No. 1, pp. 102-103, Jun. 1974.
Richman, MOS Field Effect Transistors and Integrated Circuits, (Wiley, N.Y., 1973), pp. 200-212.

Affiliated with

Also associated with

Rating

Silicon gate MOS ROM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon gate MOS ROM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon gate MOS ROM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-866115