Stock material or miscellaneous articles – All metal or with adjacent metals – Composite; i.e. – plural – adjacent – spatially distinct metal...
Reexamination Certificate
1999-01-29
2001-08-21
Jones, Deborah (Department: 1775)
Stock material or miscellaneous articles
All metal or with adjacent metals
Composite; i.e., plural, adjacent, spatially distinct metal...
C428S446000, C428S447000, C428S688000, C428S930000, C438S460000, C438S959000, C438S974000, C156S060000, C117S013000, C117S019000
Reexamination Certificate
active
06277501
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a silicon epitaxial wafer and a manufacturing method therefor, which involves the improvement of a silicon epitaxial wafer (hereinafter referred to as an epi-wafer) that has on a prescribed surface a gas-phase-grown epitaxial layer, and is provided for the fabrication of LSI and VLSI semiconductor devices and the like, and which is capable of capturing inside the wafer a variety of impurities acquired during various heat treatments in LSI, VLSI and other device fabrication processes, can enhance the gettering capabilities of the wafer without performing any process that can be expected to produce a post-wafering EG (Extrinsic-Gettering) effect in the wafer, and is capable of exhibiting a sufficient IG (Intrinsic-Gettering) effect even in a low-temperature device fabrication process of under approximately 1080° C., in accordance with manufacturing, whereby a wafer is sliced from the silicon single crystal ingot, which is pulled by controlling the oxygen concentration of the single crystal to a prescribed level, and at the same time intentionally controlling the carbon concentration to a prescribed high level, when a silicon single crystal is pulled using the Czochralski method, or the magnetic Czochralski method (hereinafter referred to simply as the CZ method), undergoes wafer processing, and, as likely as not, is subjected to further low-temperature annealing for a predetermined short period of time, followed by mirror-finish polishing, and epitaxial growth.
DESCRIPTION OF THE PRIOR ART
In the fabrication of LSI, VLSI and other device elements, generally, a silicon wafer sliced from a single-crystal ingot of silicon grown using the CZ method is mainly utilized as the substrate therefor. In recent years, the increase in the degree of integration of semiconductor devices in line with the raising of device chip performance, and the scaling down of device structures has been remarkable, rapid progress has been made in achieving high value added devices, and manufacturing costs have also risen abruptly in line therewith.
Under such conditions, the demand to improve the yield of final device products has become stronger than ever before. Meanwhile, the silicon wafer, which is the substrate of the device wafer, must of course possess high-quality crystallinity and electrical properties capable of coping with high density devices, and the supply of low-cost silicon wafers is also becoming an urgent task.
As for the silicon wafers used in large numbers in the above-mentioned application, in the past, after undergoing wafering by being sliced from a single-crystal ingot of silicon pulled using the CZ method, it was common for a wafer to undergo mirror-finish polishing on the front side only after it had been subjected to EG processing, for example, PBS (Poly-Backseal), BSD (Backside-Damage), excimer laser or other processing, that could be expected to produce an EG effect on the backside.
One method for solving the problem of lowering costs, that is, as a method for reducing the number of processes, various wafer processing methods are being studied to replace the conventional EG-processed wafer mirror-finished on one side with wafers that are not subjected to EG processing and undergo mirror-finishing on both the front and back sides, that is, non-EG-processed wafers mirror-finished on both sides.
That is, as a result of being able to omit the backside EG treatment process, which uses the BSD method and PBS growth that cause damage to a wafer backside by spraying it, for example, with an SiO2 polishing solution to capture various impurities in the device processing process, and of being able to omit the numerous front-end processes required to implement the processing thereof, it is possible to achieve large cost reductions that enable production processing costs to be reduced more than those for a conventional EG-processed wafer mirror-finished on one side. And at the same time, a wafer that is mirror-finished on both sides is also advantageous in that it can achieve higher precision planarity from the standpoints of warpage, flatness and other aspects of precision than a wafer that is mirror-finished on one side.
Similarly, another method for manufacturing a low-cost wafer is a method, which, relative to conventional EG-processed wafers that are mirror-finished on one side, is finished as a non-EG-processed wafer that is mirror-finished on one side, the backside of which wafer is not subjected to any sort of EG processing. That is, with regard to the backside of the wafer, which is not used to fabricate device elements, in accordance with using an etched (etched surface finish) wafer, which has not undergone EG processing, the BSD processing process can be omitted similar to the wafer mirror-finished on both sides.
Conversely, as for the device fabrication process, Fe, Ni, Cu and other heavy metal impurities are readily generated in the high temperature processes that are typical for D-RAM, and in accordance with these heavy metal impurities, impurity defects are formed in the wafer surface and near the wafer surface, causing the degradation of various device characteristics, and in turn lowering product yield. Consequently, to remove these heavy metal impurities from the surface and near surface regions, which comprise the device active region, various EG and IG impurity capturing (gettering) procedures, typified by the above-mentioned PBS, BSD and excimer laser, have often been utilized on the backsides of wafers in the past.
Since conventional high-temperature device processes have a relatively high Well-Drive process of between 1120° C. and 1220° C., oxygen precipitation, which is a cause of BMD, occurs relatively readily during device processing heat treatment, and because sufficient BMD are formed for gettering device impurities in the bulk inside a wafer, IG, such as N-IG (Natural-IG), which depends on EG, and DZ (Denuded Zone)-IG, have been widely utilized.
As for device processing of the future, it is clear that from now on progress will be made in lowering the temperature of processes that use design rule downscaling and high energy ion implantation in line with the move toward denser 256 MB, 1 GB integration, and in accordance with this lower temperature, the formation of BMD during device processing is expected to become difficult, making it impossible to achieve a sufficient IG effect.
In this way, although the amount of impurities generated in a device will be reduced somewhat in line with lowering the process temperature, it is believed that the generation of heavy metal impurities from high-energy ion implanting and the like will be hard to avoid, and that gettering technology will be essential.
Further, with regard to capturing heavy metal impurities using EG, it is inevitable that wafer precision, that is, high-precision planarity represented by flatness, warpage and the like, will be required more than ever for highly integrated devices of the future. In this case, if the high likelihood of the use of two-sided mirror-finished wafers capable of achieving high-precision planarity is taken into consideration, it is highly possible that EG-type gettering will not be applicable, and that it will become increasingly necessary to ensure gettering capabilities using IG.
Further, in the fabrication of a highly-integrated, high-performance device, high integrity is required of the crystalline quality characteristics and electrical quality characteristics of the wafer surface and near surface layer that correspond to the active electrical area, which affects device reliability and yields. In particular, the integrity of the surface and near surface of the wafer will obviously be required for wafers slated for high-performance, highly-integrated D-RAM semiconductor devices typical of the so-called personal computers and game machines, demand for which is expected to increase rapidly in the future.
Typical methods for solving this problem have coped by making the silicon wafer highly pure, and enhancing the integrity th
Bahta Abraham
Breiner & Breiner L.L.C.
Jones Deborah
Sumitomo Metal Industries Ltd.
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